Commit 8a224261 authored by Huang Rui's avatar Huang Rui Committed by Ingo Molnar
Browse files

perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support 



AMD Carrizo (Family 15h, Model 60h) introduces a time-stamp counter
which is indicated by CPUID.8000_0001H:ECX[27]. It increments at a 100
MHz rate in all P-states, and C states, S0, or S1. The frequency is
about 100MHz. This counter will be used to calculate processor power
and other parts. So add an interface into the MSR PMU to get the PTSC
counter value.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bp@suse.de>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Jacob Shin <jacob.w.shin@gmail.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <rric@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1454056197-5893-2-git-send-email-ray.huang@amd.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent c7afba32

arch/x86/events/msr.c

+8 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ enum perf_msr_id { 
	PERF_MSR_MPERF			= 2,

	PERF_MSR_PPERF			= 3,

	PERF_MSR_SMI			= 4,

	PERF_MSR_PTSC			= 5,



	PERF_MSR_EVENT_MAX,

};
@@ -15,6 +16,11 @@ static bool test_aperfmperf(int idx) 
	return boot_cpu_has(X86_FEATURE_APERFMPERF);

}



static bool test_ptsc(int idx)

{

	return boot_cpu_has(X86_FEATURE_PTSC);

}



static bool test_intel(int idx)

{

	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
@@ -74,6 +80,7 @@ PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01"); 
PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");

PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");

PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");

PMU_EVENT_ATTR_STRING(ptsc,  evattr_ptsc,  "event=0x05");



static struct perf_msr msr[] = {

	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },
@@ -81,6 +88,7 @@ static struct perf_msr msr[] = { 
	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },

	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },

	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },

	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },

};



static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ 
#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */

#define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */

#define X86_FEATURE_BPEXT	(6*32+26) /* data breakpoint extension */

#define X86_FEATURE_PTSC	( 6*32+27) /* performance time-stamp counter */

#define X86_FEATURE_PERFCTR_L2	( 6*32+28) /* L2 performance counter extensions */

#define X86_FEATURE_MWAITX	( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -326,6 +326,7 @@ 
#define MSR_F15H_PERF_CTR		0xc0010201

#define MSR_F15H_NB_PERF_CTL		0xc0010240

#define MSR_F15H_NB_PERF_CTR		0xc0010241

#define MSR_F15H_PTSC			0xc0010280

#define MSR_F15H_IC_CFG			0xc0011021



/* Fam 10h MSRs */

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