dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings

# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI PRU-ICSS Local Interrupt Controller

maintainers:

  - Suman Anna <s-anna@ti.com>

description: |

  Each PRU-ICSS has a single interrupt controller instance that is common

  to all the PRU cores. Most interrupt controllers can route 64 input events

  which are then mapped to 10 possible output interrupts through two levels

  of mapping. The input events can be triggered by either the PRUs and/or

  various other PRUSS internal and external peripherals. The first 2 output

  interrupts (0, 1) are fed exclusively to the internal PRU cores, with the

  remaining 8 (2 through 9) connected to external interrupt controllers

  including the MPU and/or other PRUSS instances, DSPs or devices.

  The property "ti,irqs-reserved" is used for denoting the connection

  differences on the output interrupts 2 through 9. If this property is not

  defined, it implies that all the PRUSS INTC output interrupts 2 through 9

  (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt

  controller.

  The K3 family of SoCs can handle 160 input events that can be mapped to 20

  different possible output interrupts. The additional output interrupts (10

  through 19) are connected to new sub-modules within the ICSSG instances.

  This interrupt-controller node should be defined as a child node of the

  corresponding PRUSS node. The node should be named "interrupt-controller".

properties:

  compatible:

    enum:

      - ti,pruss-intc

      - ti,icssg-intc

    description: |

      Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,

                              AM335x family of SoCs,

                              AM437x family of SoCs,

                              AM57xx family of SoCs

                              66AK2G family of SoCs

      Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs

  reg:

    maxItems: 1

  interrupts:

    minItems: 1

    maxItems: 8

    description: |

      All the interrupts generated towards the main host processor in the SoC.

      A shared interrupt can be skipped if the desired destination and usage is

      by a different processor/device.

  interrupt-names:

    minItems: 1

    maxItems: 8

    items:

      pattern: host_intr[0-7]

    description: |

      Should use one of the above names for each valid host event interrupt

      connected to Arm interrupt controller, the name should match the

      corresponding host event interrupt number.

  interrupt-controller: true

  "#interrupt-cells":

    const: 3

    description: |

      Client users shall use the PRU System event number (the interrupt source

      that the client is interested in) [cell 1], PRU channel [cell 2] and PRU

      host_event (target) [cell 3] as the value of the interrupts property in

      their node.  The system events can be mapped to some output host

      interrupts through 2 levels of many-to-one mapping i.e. events to channel

      mapping and channels to host interrupts so through this property entire

      mapping is provided.

  ti,irqs-reserved:

    $ref: /schemas/types.yaml#definitions/uint8

    description: |

      Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC

      output interrupts 2 through 9) that are not connected to the Arm interrupt

      controller or are shared and used by other devices or processors in the

      SoC. Define this property when any of 8 interrupts should not be handled

      by Arm interrupt controller.

        Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt

              connected to MPU

            - AM65x and J721E SoCs have "host_intr5", "host_intr6" and

              "host_intr7" interrupts connected to MPU, and other ICSSG

              instances.

required:

 - compatible

 - reg

 - interrupts

 - interrupt-names

 - interrupt-controller

 - "#interrupt-cells"

additionalProperties: false

examples:

  - |

    /* AM33xx PRU-ICSS */

    pruss: pruss@0 {

        compatible = "ti,am3356-pruss";

        reg = <0x0 0x80000>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;

        pruss_intc: interrupt-controller@20000 {

            compatible = "ti,pruss-intc";

            reg = <0x20000 0x2000>;

            interrupts = <20 21 22 23 24 25 26 27>;

            interrupt-names = "host_intr0", "host_intr1",

                              "host_intr2", "host_intr3",

                              "host_intr4", "host_intr5",

                              "host_intr6", "host_intr7";

            interrupt-controller;

            #interrupt-cells = <3>;

        };

    };

  - |

    /* AM4376 PRU-ICSS */

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pruss@0 {

        compatible = "ti,am4376-pruss";

        reg = <0x0 0x40000>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;

        interrupt-controller@20000 {

            compatible = "ti,pruss-intc";

            reg = <0x20000 0x2000>;

            interrupt-controller;

            #interrupt-cells = <3>;

            interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "host_intr0", "host_intr1",

                              "host_intr2", "host_intr3",

                              "host_intr4",

                              "host_intr6", "host_intr7";

            ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */

        };

    };