Merge commit '70c8f01a' into dt3-base

* Freescale IMX25 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

and usage.

CONFIG bits definition:

PAD_CTL_HYS			(1 << 8)

PAD_CTL_PKE			(1 << 7)

PAD_CTL_PUE			(1 << 6)

PAD_CTL_PUS_100K_DOWN		(0 << 4)

PAD_CTL_PUS_47K_UP		(1 << 4)

PAD_CTL_PUS_100K_UP		(2 << 4)

PAD_CTL_PUS_22K_UP		(3 << 4)

PAD_CTL_ODE_CMOS		(0 << 3)

PAD_CTL_ODE_OPENDRAIN		(1 << 3)

PAD_CTL_DSE_NOMINAL		(0 << 1)

PAD_CTL_DSE_HIGH		(1 << 1)

PAD_CTL_DSE_MAX			(2 << 1)

PAD_CTL_SRE_FAST		(1 << 0)

PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx25-pinfunc.h in device tree source folder for all available

imx25 PIN_FUNC_ID.

  CONFIG can be 0 or 1, meaning Pullup disable/enable.

The iomux controller has gpio child nodes which are embedded in the iomux

control registers. They have to be defined as child nodes of the iomux device

node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"

properties for the iomux device node are required.

Example:

iomuxc: iomuxc@10015000 {

	compatible = "fsl,imx27-iomuxc";

	reg = <0x10015000 0x600>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;

	gpio1: gpio@10015000 {

		...

	};

	...

	uart {

		pinctrl_uart1: uart-1 {

iomuxc: iomuxc@10015000 {

	compatible = "fsl,imx27-iomuxc";

	reg = <0x10015000 0x600>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges;

	gpio1: gpio@10015000 {

		...

	};

	...

	uart {

		pinctrl_uart1: uart-1 {

Qualcomm MSM8x74 TLMM block

Required properties:

- compatible: "qcom,msm8x74-pinctrl"

- reg: Should be the base address and length of the TLMM block.

- interrupts: Should be the parent IRQ of the TLMM block.

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells: Should be two.

- gpio-controller: Marks the device node as a GPIO controller.

- #gpio-cells : Should be two.

                The first cell is the gpio pin number and the

                second cell is used for optional parameters.

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for

a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".

Qualcomm's pin configuration nodes act as a container for an abitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those pin(s)/group(s), and various pin configuration

parameters, such as pull-up, drive strength, etc.

The name of each subnode is not important; all subnodes should be enumerated

and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

 pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.

Non-empty subnodes must specify the 'pins' property.

Note that not all properties are valid for all pins.

Valid values for qcom,pins are:

  gpio0-gpio145

    Supports mux, bias and drive-strength

  sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data

    Supports bias and drive-strength

Valid values for qcom,function are:

  blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus

  (Note that this is not yet the complete list of functions)

Example:

	msmgpio: pinctrl@fd510000 {

		compatible = "qcom,msm8x74-pinctrl";

		reg = <0xfd510000 0x4000>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <0 208 0>;

		pinctrl-names = "default";

		pinctrl-0 = <&uart2_default>;

		uart2_default: uart2_default {

			mux {

				qcom,pins = "gpio4", "gpio5";

				qcom,function = "blsp_uart2";

			};

			tx {

				qcom,pins = "gpio4";

				drive-strength = <4>;

				bias-disable;

			};

			rx {

				qcom,pins = "gpio5";

				drive-strength = <2>;

				bias-pull-up;

			};

		};

	};

  - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden

    otherwise. Should be 3.

  - interrupts-extended: Specify the interrupts associated with external

    IRQ pins. This property is mandatory when the PFC handles GPIOs and

    forbidden otherwise. When specified, it must contain one interrupt per

    external IRQ, sorted by external IRQ number.

The PFC node also acts as a container for pin configuration nodes. Please refer

to pinctrl-bindings.txt in this directory for the definition of the term "pin

configuration node" and for the common pinctrl bindings used by client devices.

		      <0xe605801c 0x1c>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupts-extended =

			<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,

			<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,

			<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,

			<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,

			<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,

			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,

			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,

			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;

	};

Example 2: A GPIO LED node that references a GPIO

config PINCTRL_IMX27

	bool "IMX27 pinctrl driver"

	depends on OF

	depends on SOC_IMX27

	select PINCTRL_IMX1_CORE

	help

	  Say Y here to enable the imx27 pinctrl driver

config PINCTRL_IMX25

        bool "IMX25 pinctrl driver"

        depends on OF

        depends on SOC_IMX25

        select PINCTRL_IMX

        help

          Say Y here to enable the imx25 pinctrl driver

config PINCTRL_IMX35

	bool "IMX35 pinctrl driver"

	depends on OF

	depends on SOC_IMX35

	select PINCTRL_IMX

	help

config PINCTRL_IMX50

	bool "IMX50 pinctrl driver"

	depends on OF

	depends on SOC_IMX50

	select PINCTRL_IMX

	help

config PINCTRL_IMX51

	bool "IMX51 pinctrl driver"

	depends on OF

	depends on SOC_IMX51

	select PINCTRL_IMX

	help

config PINCTRL_IMX53

	bool "IMX53 pinctrl driver"

	depends on OF

	depends on SOC_IMX53

	select PINCTRL_IMX

	help

config PINCTRL_IMX6Q

	bool "IMX6Q/DL pinctrl driver"

	depends on OF

	depends on SOC_IMX6Q

	select PINCTRL_IMX

	help

config PINCTRL_IMX6SL

	bool "IMX6SL pinctrl driver"

	depends on OF

	depends on SOC_IMX6SL

	select PINCTRL_IMX

	help

config PINCTRL_VF610

	bool "Freescale Vybrid VF610 pinctrl driver"

	depends on OF

	depends on SOC_VF610

	select PINCTRL_IMX

	help

	bool

	select PINCTRL_MXS

config PINCTRL_MSM

	bool

	select PINMUX

	select PINCONF

	select GENERIC_PINCONF

config PINCTRL_MSM8X74

	bool "Qualcomm 8x74 pin controller driver"

	depends on OF && OF_IRQ

	select PINCTRL_MSM

config PINCTRL_NOMADIK

	bool "Nomadik pin controller driver"

	depends on ARCH_U8500 || ARCH_NOMADIK