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Add support to use McSPI controller as SPI slave. In slave mode, DMA TX completion does not mean entire data has been shifted out as data might still be stuck in FIFO waiting for master to clock the bus. Therefore, add an IRQ handler for slave mode to know when entire data in FIFO has been shifted out. Signed-off-by:Vignesh R <vigneshr@ti.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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