Commit 89e4acf7 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-dt-clkdep-5.4' of... 

Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree update with new clocks:
 - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
   device tree support.
 - Add DSP device tree support for i.MX8QXP SoC.

* tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8qxp: Add DSP DT node
  arm64: dts: imx8mn: Add cpu-freq support
  arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
  arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
  arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
  arm64: dts: imx8mn: Add gpio-ranges property
  arm64: dts: freescale: Add i.MX8MN dtsi support
  clk: imx8: Add DSP related clocks
  clk: imx: Add support for i.MX8MN clock driver
  clk: imx: Add API for clk unregister when driver probe fail
  clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
  dt-bindings: imx: Add clock binding doc for i.MX8MN

Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0c89d4da cd42fa17

Documentation/devicetree/bindings/clock/imx8mn-clock.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8M Nano Clock Control Module Binding



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description: |

  NXP i.MX8M Nano clock control module is an integrated clock controller, which

  generates and supplies to all modules.



properties:

  compatible:

    const: fsl,imx8mn-ccm



  reg:

    maxItems: 1



  clocks:

    items:

      - description: 32k osc

      - description: 24m osc

      - description: ext1 clock input

      - description: ext2 clock input

      - description: ext3 clock input

      - description: ext4 clock input



  clock-names:

    items:

      - const: osc_32k

      - const: osc_24m

      - const: clk_ext1

      - const: clk_ext2

      - const: clk_ext3

      - const: clk_ext4



  '#clock-cells':

    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h

      for the full list of i.MX8M Nano clock IDs.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



examples:

  # Clock Control Module node:

  - |

    clk: clock-controller@30380000 {

        compatible = "fsl,imx8mn-ccm";

        reg = <0x0 0x30380000 0x0 0x10000>;

        #clock-cells = <1>;

        clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,

                 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;

        clock-names = "osc_32k", "osc_24m", "clk_ext1",

                      "clk_ext2", "clk_ext3", "clk_ext4";

    };



  # Required external clocks for Clock Control Module node:

  - |

    osc_32k: clock-osc-32k {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <32768>;

        clock-output-names = "osc_32k";

    };



    osc_24m: clock-osc-24m {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <24000000>;

        clock-output-names = "osc_24m";

    };



    clk_ext1: clock-ext1 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <133000000>;

        clock-output-names = "clk_ext1";

    };



    clk_ext2: clock-ext2 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <133000000>;

        clock-output-names = "clk_ext2";

    };



    clk_ext3: clock-ext3 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <133000000>;

        clock-output-names = "clk_ext3";

    };



    clk_ext4: clock-ext4 {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency= <133000000>;

        clock-output-names = "clk_ext4";

    };



...

arch/arm64/boot/dts/freescale/Makefile

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@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb 
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb



dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb

arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2019 NXP

 */



/dts-v1/;



#include "imx8mn.dtsi"



/ {

	model = "NXP i.MX8MNano DDR4 EVK board";

	compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";



	chosen {

		stdout-path = &uart2;

	};



	reg_usdhc2_vmmc: regulator-usdhc2 {

		compatible = "regulator-fixed";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;

		regulator-name = "VSD_3V3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;

		enable-active-high;

	};

};



&A53_0 {

	cpu-supply = <&buck2_reg>;

};



&iomuxc {

	pinctrl-names = "default";



	pinctrl_fec1: fec1grp {

		fsl,pins = <

			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3

			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3

			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f

			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f

			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f

			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f

			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91

			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91

			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91

			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91

			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f

			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91

			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91

			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f

			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19

		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3

			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3

		>;

	};



	pinctrl_pmic: pmicirq {

		fsl,pins = <

			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41

		>;

	};



	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {

		fsl,pins = <

			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140

			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140

		>;

	};



	pinctrl_usdhc2_gpio: usdhc2grpgpio {

		fsl,pins = <

			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4

		>;

	};



	pinctrl_usdhc2: usdhc2grp {

		fsl,pins = <

			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190

			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0

			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0

			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0

			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0

			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0

			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0

		>;

	};



	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {

		fsl,pins = <

			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194

			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4

			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4

			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4

			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4

			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4

			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0

		>;

	};



	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {

		fsl,pins = <

			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196

			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6

			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6

			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6

			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6

			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6

			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0

		>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <

			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190

			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0

			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0

			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0

			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0

			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0

			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0

			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0

			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0

			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0

			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190

		>;

	};



	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {

		fsl,pins = <

			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194

			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4

			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4

			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4

			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4

			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4

			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4

			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4

			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4

			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4

			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194

		>;

	};



	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {

		fsl,pins = <

			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196

			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6

			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6

			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6

			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6

			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6

			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6

			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6

			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6

			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6

			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196

		>;

	};



	pinctrl_wdog: wdoggrp {

		fsl,pins = <

			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6

		>;

	};

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec1>;

	phy-mode = "rgmii-id";

	phy-handle = <&ethphy0>;

	fsl,magic-packet;

	status = "okay";



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@0 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <0>;

			at803x,led-act-blind-workaround;

			at803x,eee-disabled;

			at803x,vddio-1p8v;

		};

	};

};



&i2c1 {

	clock-frequency = <400000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1>;

	status = "okay";



	pmic@4b {

		compatible = "rohm,bd71847";

		reg = <0x4b>;

		pinctrl-0 = <&pinctrl_pmic>;

		interrupt-parent = <&gpio1>;

		interrupts = <3 GPIO_ACTIVE_LOW>;

		rohm,reset-snvs-powered;



		regulators {

			buck1_reg: BUCK1 {

				regulator-name = "BUCK1";

				regulator-min-microvolt = <700000>;

				regulator-max-microvolt = <1300000>;

				regulator-boot-on;

				regulator-always-on;

				regulator-ramp-delay = <1250>;

			};



			buck2_reg: BUCK2 {

				regulator-name = "BUCK2";

				regulator-min-microvolt = <700000>;

				regulator-max-microvolt = <1300000>;

				regulator-boot-on;

				regulator-always-on;

				regulator-ramp-delay = <1250>;

			};



			buck3_reg: BUCK3 {

				// BUCK5 in datasheet

				regulator-name = "BUCK3";

				regulator-min-microvolt = <700000>;

				regulator-max-microvolt = <1350000>;

			};



			buck4_reg: BUCK4 {

				// BUCK6 in datasheet

				regulator-name = "BUCK4";

				regulator-min-microvolt = <3000000>;

				regulator-max-microvolt = <3300000>;

				regulator-boot-on;

				regulator-always-on;

			};



			buck5_reg: BUCK5 {

				// BUCK7 in datasheet

				regulator-name = "BUCK5";

				regulator-min-microvolt = <1605000>;

				regulator-max-microvolt = <1995000>;

				regulator-boot-on;

				regulator-always-on;

			};



			buck6_reg: BUCK6 {

				// BUCK8 in datasheet

				regulator-name = "BUCK6";

				regulator-min-microvolt = <800000>;

				regulator-max-microvolt = <1400000>;

				regulator-boot-on;

				regulator-always-on;

			};



			ldo1_reg: LDO1 {

				regulator-name = "LDO1";

				regulator-min-microvolt = <3000000>;

				regulator-max-microvolt = <3300000>;

				regulator-boot-on;

				regulator-always-on;

			};



			ldo2_reg: LDO2 {

				regulator-name = "LDO2";

				regulator-min-microvolt = <900000>;

				regulator-max-microvolt = <900000>;

				regulator-boot-on;

				regulator-always-on;

			};



			ldo3_reg: LDO3 {

				regulator-name = "LDO3";

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <3300000>;

				regulator-boot-on;

				regulator-always-on;

			};



			ldo4_reg: LDO4 {

				regulator-name = "LDO4";

				regulator-min-microvolt = <900000>;

				regulator-max-microvolt = <1800000>;

				regulator-boot-on;

				regulator-always-on;

			};



			ldo6_reg: LDO6 {

				regulator-name = "LDO6";

				regulator-min-microvolt = <900000>;

				regulator-max-microvolt = <1800000>;

				regulator-boot-on;

				regulator-always-on;

			};

		};

	};

};



&snvs_pwrkey {

	status = "okay";

};



&uart2 { /* console */

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2>;

	status = "okay";

};



&usdhc2 {

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;

	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;

	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;

	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;

	bus-width = <4>;

	vmmc-supply = <&reg_usdhc2_vmmc>;

	status = "okay";

};



&usdhc3 {

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc3>;

	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;

	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;

	bus-width = <8>;

	non-removable;

	status = "okay";

};



&wdog1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_wdog>;

	fsl,ext-reset-output;

	status = "okay";

};

arch/arm64/boot/dts/freescale/imx8mn.dtsi

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arch/arm64/boot/dts/freescale/imx8qxp-mek.dts

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@@ -230,3 +230,7 @@ 
		>;

	};

};



&adma_dsp {

	status = "okay";

};

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