Commit 89da2ba9 authored by YueHaibing's avatar YueHaibing Committed by Bjorn Andersson
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soc: qcom: Fix llcc-qcom definitions to include 



commit 99356b03 ("soc: qcom: Make llcc-qcom a generic driver") move
these out of llcc-qcom.h, make the building fails:

drivers/edac/qcom_edac.c:86:40: error: array type has incomplete element type struct llcc_edac_reg_data
 static const struct llcc_edac_reg_data edac_reg_data[] = {
                                        ^~~~~~~~~~~~~
drivers/edac/qcom_edac.c:87:3: error: array index in non-array initializer
  [LLCC_DRAM_CE] = {
   ^~~~~~~~~~~~
drivers/edac/qcom_edac.c:87:3: note: (near initialization for edac_reg_data)
drivers/edac/qcom_edac.c:88:3: error: field name not in record or union initializer
   .name = "DRAM Single-bit",
...
drivers/edac/qcom_edac.c:169:51: warning: struct llcc_drv_data declared inside parameter
 list will not be visible outside of this definition or declaration
 qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv)
                                                   ^~~~~~~~~~~~~

This patch move the needed definitions back to include.

Reported-by: default avatarHulk Robot <hulkci@huawei.com>
Fixes: 99356b03 ("soc: qcom: Make llcc-qcom a generic driver")
Signed-off-by: default avatarYueHaibing <yuehaibing@huawei.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent b1d52244

drivers/soc/qcom/llcc-qcom.c

+0 −50
Original line number Diff line number Diff line
@@ -86,56 +86,6 @@ struct llcc_slice_config { 
	bool activate_on_init;

};



/**

 * llcc_drv_data - Data associated with the llcc driver

 * @regmap: regmap associated with the llcc device

 * @bcast_regmap: regmap associated with llcc broadcast offset

 * @cfg: pointer to the data structure for slice configuration

 * @lock: mutex associated with each slice

 * @cfg_size: size of the config data table

 * @max_slices: max slices as read from device tree

 * @num_banks: Number of llcc banks

 * @bitmap: Bit map to track the active slice ids

 * @offsets: Pointer to the bank offsets array

 * @ecc_irq: interrupt for llcc cache error detection and reporting

 */

struct llcc_drv_data {

	struct regmap *regmap;

	struct regmap *bcast_regmap;

	const struct llcc_slice_config *cfg;

	struct mutex lock;

	u32 cfg_size;

	u32 max_slices;

	u32 num_banks;

	unsigned long *bitmap;

	u32 *offsets;

	int ecc_irq;

};



/**

 * llcc_edac_reg_data - llcc edac registers data for each error type

 * @name: Name of the error

 * @synd_reg: Syndrome register address

 * @count_status_reg: Status register address to read the error count

 * @ways_status_reg: Status register address to read the error ways

 * @reg_cnt: Number of registers

 * @count_mask: Mask value to get the error count

 * @ways_mask: Mask value to get the error ways

 * @count_shift: Shift value to get the error count

 * @ways_shift: Shift value to get the error ways

 */

struct llcc_edac_reg_data {

	char *name;

	u64 synd_reg;

	u64 count_status_reg;

	u64 ways_status_reg;

	u32 reg_cnt;

	u32 count_mask;

	u32 ways_mask;

	u8  count_shift;

	u8  ways_shift;

};



struct qcom_llcc_config {

	const struct llcc_slice_config *sct_data;

	int size;

include/linux/soc/qcom/llcc-qcom.h

+50 −0
Original line number Diff line number Diff line
@@ -37,6 +37,56 @@ struct llcc_slice_desc { 
	size_t slice_size;

};



/**

 * llcc_edac_reg_data - llcc edac registers data for each error type

 * @name: Name of the error

 * @synd_reg: Syndrome register address

 * @count_status_reg: Status register address to read the error count

 * @ways_status_reg: Status register address to read the error ways

 * @reg_cnt: Number of registers

 * @count_mask: Mask value to get the error count

 * @ways_mask: Mask value to get the error ways

 * @count_shift: Shift value to get the error count

 * @ways_shift: Shift value to get the error ways

 */

struct llcc_edac_reg_data {

	char *name;

	u64 synd_reg;

	u64 count_status_reg;

	u64 ways_status_reg;

	u32 reg_cnt;

	u32 count_mask;

	u32 ways_mask;

	u8  count_shift;

	u8  ways_shift;

};



/**

 * llcc_drv_data - Data associated with the llcc driver

 * @regmap: regmap associated with the llcc device

 * @bcast_regmap: regmap associated with llcc broadcast offset

 * @cfg: pointer to the data structure for slice configuration

 * @lock: mutex associated with each slice

 * @cfg_size: size of the config data table

 * @max_slices: max slices as read from device tree

 * @num_banks: Number of llcc banks

 * @bitmap: Bit map to track the active slice ids

 * @offsets: Pointer to the bank offsets array

 * @ecc_irq: interrupt for llcc cache error detection and reporting

 */

struct llcc_drv_data {

	struct regmap *regmap;

	struct regmap *bcast_regmap;

	const struct llcc_slice_config *cfg;

	struct mutex lock;

	u32 cfg_size;

	u32 max_slices;

	u32 num_banks;

	unsigned long *bitmap;

	u32 *offsets;

	int ecc_irq;

};



#if IS_ENABLED(CONFIG_QCOM_LLCC)

/**

 * llcc_slice_getd - get llcc slice descriptor

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