Commit 89c683cd authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf tooling fixes from Ingo  Molnar:
 "These are all perf tooling changes: most of them are fixes.

  Note that the large CPU count related fixes go beyond regression
  fixes, but the IPI-flood symptoms are severe enough that I think
  justifies their inclusion"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (38 commits)
  perf vendor events s390: Remove name from L1D_RO_EXCL_WRITES description
  perf vendor events s390: Fix counter long description for DTLB1_GPAGE_WRITES
  libtraceevent: Allow custom libdir path
  perf header: Fix false warning when there are no duplicate cache entries
  perf metricgroup: Fix printing event names of metric group with multiple events
  perf/x86/pmu-events: Fix Kernel_Utilization metric
  perf top: Do not bail out when perf_env__read_cpuid() returns ENOSYS
  perf arch: Make the default get_cpuid() return compatible error
  tools headers kvm: Sync linux/kvm.h with the kernel sources
  tools headers UAPI: Update tools's copy of drm.h headers
  tools headers UAPI: Sync drm/i915_drm.h with the kernel sources
  perf inject: Fix processing of ID index for injected instruction tracing
  perf report: Bail out --mem-mode if mem info is not available
  perf report: Make -F more strict like -s
  perf report/top TUI: Replace pr_err() with ui__error()
  libtraceevent: Copy pkg-config file to output folder when using O=
  libtraceevent: Fix lib installation with O=
  perf kvm: Clarify the 'perf kvm' -i and -o command line options
  tools arch x86: Sync asm/cpufeatures.h with the kernel sources
  perf beauty: Add CLEAR_SIGHAND support for clone's flags arg
  ...
parents 9e8a0d5f 57e04eed

tools/arch/arm/include/uapi/asm/kvm.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -131,8 +131,9 @@ struct kvm_vcpu_events { 
	struct {

	struct {

		__u8 serror_pending;

		__u8 serror_pending;

		__u8 serror_has_esr;

		__u8 serror_has_esr;

		__u8 ext_dabt_pending;

		/* Align it to 8 bytes */

		/* Align it to 8 bytes */

		__u8 pad[6];

		__u8 pad[5];

		__u64 serror_esr;

		__u64 serror_esr;

	} exception;

	} exception;

	__u32 reserved[12];

	__u32 reserved[12];

tools/arch/arm64/include/uapi/asm/kvm.h

+4 −1
Original line number Original line Diff line number Diff line
@@ -164,8 +164,9 @@ struct kvm_vcpu_events { 
	struct {

	struct {

		__u8 serror_pending;

		__u8 serror_pending;

		__u8 serror_has_esr;

		__u8 serror_has_esr;

		__u8 ext_dabt_pending;

		/* Align it to 8 bytes */

		/* Align it to 8 bytes */

		__u8 pad[6];

		__u8 pad[5];

		__u64 serror_esr;

		__u64 serror_esr;

	} exception;

	} exception;

	__u32 reserved[12];

	__u32 reserved[12];
@@ -323,6 +324,8 @@ struct kvm_vcpu_events { 
#define KVM_ARM_VCPU_TIMER_CTRL		1

#define KVM_ARM_VCPU_TIMER_CTRL		1

#define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0

#define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0

#define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1

#define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1

#define KVM_ARM_VCPU_PVTIME_CTRL	2

#define   KVM_ARM_VCPU_PVTIME_IPA	0





/* KVM_IRQ_LINE irq field index values */

/* KVM_IRQ_LINE irq field index values */

#define KVM_ARM_IRQ_VCPU2_SHIFT		28

#define KVM_ARM_IRQ_VCPU2_SHIFT		28

tools/arch/powerpc/include/uapi/asm/kvm.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -667,6 +667,8 @@ struct kvm_ppc_cpu_char { 




/* PPC64 eXternal Interrupt Controller Specification */

/* PPC64 eXternal Interrupt Controller Specification */

#define KVM_DEV_XICS_GRP_SOURCES	1	/* 64-bit source attributes */

#define KVM_DEV_XICS_GRP_SOURCES	1	/* 64-bit source attributes */

#define KVM_DEV_XICS_GRP_CTRL		2

#define   KVM_DEV_XICS_NR_SERVERS	1





/* Layout of 64-bit source attribute values */

/* Layout of 64-bit source attribute values */

#define  KVM_XICS_DESTINATION_SHIFT	0

#define  KVM_XICS_DESTINATION_SHIFT	0
@@ -683,6 +685,7 @@ struct kvm_ppc_cpu_char { 
#define KVM_DEV_XIVE_GRP_CTRL		1

#define KVM_DEV_XIVE_GRP_CTRL		1

#define   KVM_DEV_XIVE_RESET		1

#define   KVM_DEV_XIVE_RESET		1

#define   KVM_DEV_XIVE_EQ_SYNC		2

#define   KVM_DEV_XIVE_EQ_SYNC		2

#define   KVM_DEV_XIVE_NR_SERVERS	3

#define KVM_DEV_XIVE_GRP_SOURCE		2	/* 64-bit source identifier */

#define KVM_DEV_XIVE_GRP_SOURCE		2	/* 64-bit source identifier */

#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG	3	/* 64-bit source identifier */

#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG	3	/* 64-bit source identifier */

#define KVM_DEV_XIVE_GRP_EQ_CONFIG	4	/* 64-bit EQ identifier */

#define KVM_DEV_XIVE_GRP_EQ_CONFIG	4	/* 64-bit EQ identifier */

tools/arch/x86/include/asm/cpufeatures.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -292,6 +292,7 @@ 
#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */

#define X86_FEATURE_RDPRU		(13*32+ 4) /* Read processor register at user level */

#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */

#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */

#define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */

#define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */

#define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */

#define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
@@ -399,5 +400,7 @@ 
#define X86_BUG_MDS			X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */

#define X86_BUG_MDS			X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */

#define X86_BUG_MSBDS_ONLY		X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */

#define X86_BUG_MSBDS_ONLY		X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */

#define X86_BUG_SWAPGS			X86_BUG(21) /* CPU is affected by speculation through SWAPGS */

#define X86_BUG_SWAPGS			X86_BUG(21) /* CPU is affected by speculation through SWAPGS */

#define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */

#define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */





#endif /* _ASM_X86_CPUFEATURES_H */
 
#endif /* _ASM_X86_CPUFEATURES_H */

tools/arch/x86/include/asm/msr-index.h

+18 −0
Original line number Original line Diff line number Diff line
@@ -93,6 +93,18 @@ 
						  * Microarchitectural Data

						  * Microarchitectural Data

						  * Sampling (MDS) vulnerabilities.

						  * Sampling (MDS) vulnerabilities.

						  */

						  */

#define ARCH_CAP_PSCHANGE_MC_NO		BIT(6)	 /*

						  * The processor is not susceptible to a

						  * machine check error due to modifying the

						  * code page size along with either the

						  * physical address or cache type

						  * without TLB invalidation.

						  */

#define ARCH_CAP_TSX_CTRL_MSR		BIT(7)	/* MSR for TSX control is available. */

#define ARCH_CAP_TAA_NO			BIT(8)	/*

						 * Not susceptible to

						 * TSX Async Abort (TAA) vulnerabilities.

						 */





#define MSR_IA32_FLUSH_CMD		0x0000010b

#define MSR_IA32_FLUSH_CMD		0x0000010b

#define L1D_FLUSH			BIT(0)	/*

#define L1D_FLUSH			BIT(0)	/*
@@ -103,6 +115,10 @@ 
#define MSR_IA32_BBL_CR_CTL		0x00000119

#define MSR_IA32_BBL_CR_CTL		0x00000119

#define MSR_IA32_BBL_CR_CTL3		0x0000011e

#define MSR_IA32_BBL_CR_CTL3		0x0000011e





#define MSR_IA32_TSX_CTRL		0x00000122

#define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */

#define TSX_CTRL_CPUID_CLEAR		BIT(1)	/* Disable TSX enumeration */



#define MSR_IA32_SYSENTER_CS		0x00000174

#define MSR_IA32_SYSENTER_CS		0x00000174

#define MSR_IA32_SYSENTER_ESP		0x00000175

#define MSR_IA32_SYSENTER_ESP		0x00000175

#define MSR_IA32_SYSENTER_EIP		0x00000176

#define MSR_IA32_SYSENTER_EIP		0x00000176
@@ -393,6 +409,8 @@ 
#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064

#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064

#define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140

#define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140

#define MSR_AMD64_OSVW_STATUS		0xc0010141

#define MSR_AMD64_OSVW_STATUS		0xc0010141

#define MSR_AMD_PPIN_CTL		0xc00102f0

#define MSR_AMD_PPIN			0xc00102f1

#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_LS_CFG		0xc0011020

#define MSR_AMD64_DC_CFG		0xc0011022

#define MSR_AMD64_DC_CFG		0xc0011022

#define MSR_AMD64_BU_CFG2		0xc001102a

#define MSR_AMD64_BU_CFG2		0xc001102a

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