mtd: pxa3xx_nand: clean up the pxa3xx timings

};

struct pxa3xx_nand_flash {

	char		*name;

	uint32_t	chip_id;

	unsigned int	page_per_block; /* Pages per block (PG_PER_BLK) */

	unsigned int	page_size;	/* Page size in bytes (PAGE_SZ) */

	unsigned int	flash_width;	/* Width of Flash memory (DWIDTH_M) */

	unsigned int	dfc_width;	/* Width of flash controller(DWIDTH_C) */

	unsigned int	num_blocks;	/* Number of physical blocks in Flash */

	struct pxa3xx_nand_timing *timing;	/* NAND Flash timing */

};

};

static struct pxa3xx_nand_flash builtin_flash_types[] = {

{ "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },

{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },

{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },

{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },

{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },

{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },

{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },

{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },

{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },

	{ 0x46ec, 16, 16, &timing[1] },

	{ 0xdaec,  8,  8, &timing[1] },

	{ 0xd7ec,  8,  8, &timing[1] },

	{ 0xa12c,  8,  8, &timing[2] },

	{ 0xb12c, 16, 16, &timing[2] },

	{ 0xdc2c,  8,  8, &timing[2] },

	{ 0xcc2c, 16, 16, &timing[2] },

	{ 0xba20, 16, 16, &timing[3] },

};

static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };

	.oobfree = { }

};

/* Define a default flash type setting serve as flash detecting only */

#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])

#define NDTR0_tCH(c)	(min((c), 7) << 19)

#define NDTR0_tCS(c)	(min((c), 7) << 16)

#define NDTR0_tWH(c)	(min((c), 7) << 11)