Commit 89ac8567 authored Aug 28, 2013 by Tuomas Tynkkynen Committed by Mike Turquette Aug 28, 2013

clk: tegra30: Don't wait for PLL_U lock bit



The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

parent 5b0dde99

drivers/clk/tegra/clk-tegra30.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -971,7 +971,7 @@ static void __init tegra30_pll_init(void)
		/* PLLU */
		clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
		0, &pll_u_params, TEGRA_PLLU \| TEGRA_PLL_HAS_CPCON \|
		TEGRA_PLL_SET_LFCON \| TEGRA_PLL_USE_LOCK,
		TEGRA_PLL_SET_LFCON,
		pll_u_freq_table,
		NULL);
		clk_register_clkdev(clk, "pll_u", NULL);

Admin message