drm/amd/display: Add DCN3 DWB (8993dee0) · Commits · 戴 / test

drivers/gpu/drm/amd/display/dc/dc_types.h

+25 −0

Original line number	Diff line number	Diff line
		@@ -475,6 +475,19 @@ enum display_content_type {
		DISPLAY_CONTENT_TYPE_GAME = 8
		};

		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		enum cm_gamut_adjust_type {
		CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
		CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
		CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
		};

		struct cm_grph_csc_adjustment {
		struct fixed31_32 temperature_matrix[12];
		enum cm_gamut_adjust_type gamut_adjust_type;
		enum cm_gamut_coef_format gamut_coef_format;
		};
		#endif
		/* writeback */
		struct dwb_stereo_params {
		bool stereo_enabled; /* false: normal mode, true: 3D stereo */
		@@ -492,9 +505,21 @@ struct dc_dwb_cnv_params {
		unsigned int crop_x; /* cropped window start x value at cnv output */
		unsigned int crop_y; /* cropped window start y value at cnv output */
		enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
		enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */
		unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
		unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
		#endif
		};

		struct dc_dwb_params {
		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		unsigned int dwbscl_black_color; /* must be in FP1.5.10 */
		unsigned int hdr_mult; /* must be in FP1.6.12 */
		struct cm_grph_csc_adjustment csc_params;
		struct dwb_stereo_params stereo_params;
		#endif
		struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
		unsigned int dest_width; /* Destination width */
		unsigned int dest_height; /* Destination height */

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c

0 → 100644

+264 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2020 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/


		#include "reg_helper.h"
		#include "resource.h"
		#include "dwb.h"
		#include "dcn30_dwb.h"


		#define REG(reg)\
		dwbc30->dwbc_regs->reg

		#define CTX \
		dwbc30->base.ctx

		#undef FN
		#define FN(reg_name, field_name) \
		dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name

		#define DC_LOGGER \
		dwbc30->base.ctx->logger

		static bool dwb3_get_caps(struct dwbc dwbc, struct dwb_caps caps)
		{
		if (caps) {
		caps->adapter_id = 0; /* we only support 1 adapter currently */
		caps->hw_version = DCN_VERSION_3_0;
		caps->num_pipes = 2;
		memset(&caps->reserved, 0, sizeof(caps->reserved));
		memset(&caps->reserved2, 0, sizeof(caps->reserved2));
		caps->sw_version = dwb_ver_2_0;
		caps->caps.support_dwb = true;
		caps->caps.support_ogam = true;
		caps->caps.support_wbscl = true;
		caps->caps.support_ocsc = false;
		caps->caps.support_stereo = true;
		return true;
		} else {
		return false;
		}
		}

		void dwb3_config_fc(struct dwbc dwbc, struct dc_dwb_params params)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		/* Set DWB source size */
		REG_UPDATE_2(FC_SOURCE_SIZE, FC_SOURCE_WIDTH, params->cnv_params.src_width,
		FC_SOURCE_HEIGHT, params->cnv_params.src_height);

		/* source size is not equal the source size, then enable cropping. */
		if (params->cnv_params.crop_en) {
		REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1);
		REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_X, params->cnv_params.crop_x);
		REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_Y, params->cnv_params.crop_y);
		REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_WIDTH, params->cnv_params.crop_width);
		REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_HEIGHT, params->cnv_params.crop_height);
		} else {
		REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0);
		}

		/* Set CAPTURE_RATE */
		REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate);

		dwb3_set_stereo(dwbc, &params->stereo_params);
		}

		bool dwb3_enable(struct dwbc dwbc, struct dc_dwb_params params)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
		DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst);

		/* Set WB_ENABLE (not double buffered; capture not enabled) */
		REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1);

		/* Set FC parameters */
		dwb3_config_fc(dwbc, params);

		/* Program color processing unit */
		dwb3_program_hdr_mult(dwbc, params);
		dwb3_set_gamut_remap(dwbc, params);
		dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);

		/* Program output denorm */
		dwb3_set_denorm(dwbc, params);

		/* Enable DWB capture enable (double buffered) */
		REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE);

		/* First pixel count */
		REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96);

		return true;
		}

		bool dwb3_disable(struct dwbc *dwbc)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		/* disable FC */
		REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);

		/* disable WB */
		REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 0);

		DC_LOG_DWB("%s dwb3_disabled at inst = %d", __func__, dwbc->inst);
		return true;
		}

		bool dwb3_update(struct dwbc dwbc, struct dc_dwb_params params)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
		unsigned int pre_locked;

		/*
		* Check if the caller has already locked DWB registers.
		* If so: assume the caller will unlock, so don't touch the lock.
		* If not: lock them for this update, then unlock after the
		* update is complete.
		*/
		REG_GET(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, &pre_locked);
		DC_LOG_DWB("%s dwb update, inst = %d", __func__, dwbc->inst);

		if (pre_locked == 0) {
		/* Lock DWB registers */
		REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 1);
		}

		/* Set FC parameters */
		dwb3_config_fc(dwbc, params);

		/* Program color processing unit */
		dwb3_program_hdr_mult(dwbc, params);
		dwb3_set_gamut_remap(dwbc, params);
		dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);

		/* Program output denorm */
		dwb3_set_denorm(dwbc, params);

		if (pre_locked == 0) {
		/* Unlock DWB registers */
		REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 0);
		}

		return true;
		}

		bool dwb3_is_enabled(struct dwbc *dwbc)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
		unsigned int dwb_enabled = 0;
		unsigned int fc_frame_capture_en = 0;

		REG_GET(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, &dwb_enabled);
		REG_GET(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, &fc_frame_capture_en);

		return ((dwb_enabled != 0) && (fc_frame_capture_en != 0));
		}

		void dwb3_set_stereo(struct dwbc *dwbc,
		struct dwb_stereo_params *stereo_params)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		if (stereo_params->stereo_enabled) {
		REG_UPDATE(FC_MODE_CTRL, FC_EYE_SELECTION, stereo_params->stereo_eye_select);
		REG_UPDATE(FC_MODE_CTRL, FC_STEREO_EYE_POLARITY, stereo_params->stereo_polarity);
		DC_LOG_DWB("%s dwb stereo enabled", __func__);
		} else {
		REG_UPDATE(FC_MODE_CTRL, FC_EYE_SELECTION, 0);
		DC_LOG_DWB("%s dwb stereo disabled", __func__);
		}
		}

		void dwb3_set_new_content(struct dwbc *dwbc,
		bool is_new_content)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		REG_UPDATE(FC_MODE_CTRL, FC_NEW_CONTENT, is_new_content);
		}

		void dwb3_set_denorm(struct dwbc dwbc, struct dc_dwb_params params)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		/* Set output format*/
		REG_UPDATE(DWB_OUT_CTRL, OUT_FORMAT, params->cnv_params.fc_out_format);

		/* Set output denorm */
		if (params->cnv_params.fc_out_format == DWB_OUT_FORMAT_32BPP_ARGB \|\|
		params->cnv_params.fc_out_format == DWB_OUT_FORMAT_32BPP_RGBA) {
		REG_UPDATE(DWB_OUT_CTRL, OUT_DENORM, params->cnv_params.out_denorm_mode);
		REG_UPDATE(DWB_OUT_CTRL, OUT_MAX, params->cnv_params.out_max_pix_val);
		REG_UPDATE(DWB_OUT_CTRL, OUT_MIN, params->cnv_params.out_min_pix_val);
		}
		}


		const struct dwbc_funcs dcn30_dwbc_funcs = {
		.get_caps = dwb3_get_caps,
		.enable = dwb3_enable,
		.disable = dwb3_disable,
		.update = dwb3_update,
		.is_enabled = dwb3_is_enabled,
		.set_stereo = dwb3_set_stereo,
		.set_new_content = dwb3_set_new_content,
		.dwb_program_output_csc = NULL,
		.dwb_ogam_set_input_transfer_func = dwb3_ogam_set_input_transfer_func, //TODO: rename
		.dwb_set_scaler = NULL,
		};

		void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,
		struct dc_context *ctx,
		const struct dcn30_dwbc_registers *dwbc_regs,
		const struct dcn30_dwbc_shift *dwbc_shift,
		const struct dcn30_dwbc_mask *dwbc_mask,
		int inst)
		{
		dwbc30->base.ctx = ctx;

		dwbc30->base.inst = inst;
		dwbc30->base.funcs = &dcn30_dwbc_funcs;

		dwbc30->dwbc_regs = dwbc_regs;
		dwbc30->dwbc_shift = dwbc_shift;
		dwbc30->dwbc_mask = dwbc_mask;
		}

		void dwb3_set_host_read_rate_control(struct dwbc *dwbc, bool host_read_delay)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		/*
		* Set maximum delay of host read access to DWBSCL LUT or OGAM LUT if there are no
		* idle cycles in HW pipeline (in number of clock cycles times 4)
		*/
		REG_UPDATE(DWB_HOST_READ_CONTROL, DWB_HOST_READ_RATE_CONTROL, host_read_delay);

		DC_LOG_DWB("%s dwb3_rate_control at inst = %d", __func__, dwbc->inst);
		}

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h

0 → 100644

+923 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c

0 → 100644

+354 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2020 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/

		#include "reg_helper.h"
		#include "fixed31_32.h"
		#include "resource.h"
		#include "basics/conversion.h"
		#include "dwb.h"
		#include "dcn30_dwb.h"
		#include "dcn30_cm_common.h"
		#include "dcn10/dcn10_cm_common.h"


		#define REG(reg)\
		dwbc30->dwbc_regs->reg

		#define CTX \
		dwbc30->base.ctx

		#undef FN
		#define FN(reg_name, field_name) \
		dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name

		#define TO_DCN30_DWBC(dwbc_base) \
		container_of(dwbc_base, struct dcn30_dwbc, base)

		static void dwb3_get_reg_field_ogam(struct dcn30_dwbc *dwbc30,
		struct dcn3_xfer_func_reg *reg)
		{
		reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
		reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
		reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
		reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
		reg->shifts.exp_region1_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
		reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
		reg->shifts.exp_region1_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
		reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

		reg->shifts.field_region_end = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_B;
		reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B;
		reg->shifts.field_region_end_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
		reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
		reg->shifts.field_region_end_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
		reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
		reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
		reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
		reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B;
		reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B;
		reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B;
		reg->masks.exp_region_start = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_B;
		reg->shifts.exp_resion_start_segment = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
		reg->masks.exp_resion_start_segment = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
		}

		/program dwb ogam RAM A/
		static void dwb3_program_ogam_luta_settings(
		struct dcn30_dwbc *dwbc30,
		const struct pwl_params *params)
		{
		struct dcn3_xfer_func_reg gam_regs;

		dwb3_get_reg_field_ogam(dwbc30, &gam_regs);

		gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B);
		gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G);
		gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R);
		gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B);
		gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G);
		gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R);
		gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B);
		gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G);
		gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R);
		gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMA_END_CNTL1_B);
		gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMA_END_CNTL2_B);
		gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMA_END_CNTL1_G);
		gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMA_END_CNTL2_G);
		gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMA_END_CNTL1_R);
		gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMA_END_CNTL2_R);
		gam_regs.offset_b = REG(DWB_OGAM_RAMA_OFFSET_B);
		gam_regs.offset_g = REG(DWB_OGAM_RAMA_OFFSET_G);
		gam_regs.offset_r = REG(DWB_OGAM_RAMA_OFFSET_R);
		gam_regs.region_start = REG(DWB_OGAM_RAMA_REGION_0_1);
		gam_regs.region_end = REG(DWB_OGAM_RAMA_REGION_32_33);
		/todo/
		cm_helper_program_gamcor_xfer_func(dwbc30->base.ctx, params, &gam_regs);
		}

		/program dwb ogam RAM B/
		static void dwb3_program_ogam_lutb_settings(
		struct dcn30_dwbc *dwbc30,
		const struct pwl_params *params)
		{
		struct dcn3_xfer_func_reg gam_regs;

		dwb3_get_reg_field_ogam(dwbc30, &gam_regs);

		gam_regs.start_cntl_b = REG(DWB_OGAM_RAMB_START_CNTL_B);
		gam_regs.start_cntl_g = REG(DWB_OGAM_RAMB_START_CNTL_G);
		gam_regs.start_cntl_r = REG(DWB_OGAM_RAMB_START_CNTL_R);
		gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMB_START_BASE_CNTL_B);
		gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMB_START_BASE_CNTL_G);
		gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMB_START_BASE_CNTL_R);
		gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_B);
		gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_G);
		gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMB_START_SLOPE_CNTL_R);
		gam_regs.start_end_cntl1_b = REG(DWB_OGAM_RAMB_END_CNTL1_B);
		gam_regs.start_end_cntl2_b = REG(DWB_OGAM_RAMB_END_CNTL2_B);
		gam_regs.start_end_cntl1_g = REG(DWB_OGAM_RAMB_END_CNTL1_G);
		gam_regs.start_end_cntl2_g = REG(DWB_OGAM_RAMB_END_CNTL2_G);
		gam_regs.start_end_cntl1_r = REG(DWB_OGAM_RAMB_END_CNTL1_R);
		gam_regs.start_end_cntl2_r = REG(DWB_OGAM_RAMB_END_CNTL2_R);
		gam_regs.offset_b = REG(DWB_OGAM_RAMB_OFFSET_B);
		gam_regs.offset_g = REG(DWB_OGAM_RAMB_OFFSET_G);
		gam_regs.offset_r = REG(DWB_OGAM_RAMB_OFFSET_R);
		gam_regs.region_start = REG(DWB_OGAM_RAMB_REGION_0_1);
		gam_regs.region_end = REG(DWB_OGAM_RAMB_REGION_32_33);

		cm_helper_program_gamcor_xfer_func(dwbc30->base.ctx, params, &gam_regs);
		}

		static enum dc_lut_mode dwb3_get_ogam_current(
		struct dcn30_dwbc *dwbc30)
		{
		enum dc_lut_mode mode;
		uint32_t state_mode;
		uint32_t ram_select;

		REG_GET(DWB_OGAM_CONTROL,
		DWB_OGAM_MODE, &state_mode);
		REG_GET(DWB_OGAM_CONTROL,
		DWB_OGAM_SELECT, &ram_select);

		if (state_mode == 0) {
		mode = LUT_BYPASS;
		} else if (state_mode == 2) {
		if (ram_select == 0)
		mode = LUT_RAM_A;
		else
		mode = LUT_RAM_B;
		} else {
		// Reserved value
		mode = LUT_BYPASS;
		BREAK_TO_DEBUGGER();
		return mode;
		}
		return mode;
		}

		static void dwb3_configure_ogam_lut(
		struct dcn30_dwbc *dwbc30,
		bool is_ram_a)
		{
		REG_UPDATE(DWB_OGAM_LUT_CONTROL,
		DWB_OGAM_LUT_READ_COLOR_SEL, 7);
		REG_UPDATE(DWB_OGAM_CONTROL,
		DWB_OGAM_SELECT, is_ram_a == true ? 0 : 1);
		REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
		}

		static void dwb3_program_ogam_pwl(struct dcn30_dwbc *dwbc30,
		const struct pwl_result_data *rgb,
		uint32_t num)
		{
		uint32_t i;

		// triple base implementation
		for (i = 0; i < num/2; i++) {
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+0].red_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+0].green_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+0].blue_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+1].red_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+1].green_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+1].blue_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+2].red_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+2].green_reg);
		REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+2].blue_reg);
		}
		}

		static bool dwb3_program_ogam_lut(
		struct dcn30_dwbc *dwbc30,
		const struct pwl_params *params)
		{
		enum dc_lut_mode current_mode;
		enum dc_lut_mode next_mode;

		if (params == NULL) {
		REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 0);
		return false;
		}

		current_mode = dwb3_get_ogam_current(dwbc30);
		if (current_mode == LUT_BYPASS \|\| current_mode == LUT_RAM_A)
		next_mode = LUT_RAM_B;
		else
		next_mode = LUT_RAM_A;

		dwb3_configure_ogam_lut(dwbc30, next_mode == LUT_RAM_A ? true : false);

		if (next_mode == LUT_RAM_A)
		dwb3_program_ogam_luta_settings(dwbc30, params);
		else
		dwb3_program_ogam_lutb_settings(dwbc30, params);

		dwb3_program_ogam_pwl(
		dwbc30, params->rgb_resulted, params->hw_points_num);

		REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2);
		REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

		return true;
		}

		bool dwb3_ogam_set_input_transfer_func(
		struct dwbc *dwbc,
		const struct dc_transfer_func *in_transfer_func_dwb_ogam)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
		bool result = false;
		struct pwl_params *dwb_ogam_lut = NULL;

		if (in_transfer_func_dwb_ogam == NULL)
		return result;

		dwb_ogam_lut = kzalloc(sizeof(*dwb_ogam_lut), GFP_KERNEL);

		if (dwb_ogam_lut) {
		cm_helper_translate_curve_to_hw_format(
		in_transfer_func_dwb_ogam,
		dwb_ogam_lut, false);

		result = dwb3_program_ogam_lut(
		dwbc30,
		dwb_ogam_lut);
		kfree(dwb_ogam_lut);
		dwb_ogam_lut = NULL;
		}

		return result;
		}

		static void dwb3_program_gamut_remap(
		struct dwbc *dwbc,
		const uint16_t *regval,
		enum cm_gamut_coef_format coef_format,
		enum cm_gamut_remap_select select)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		struct color_matrices_reg gam_regs;

		REG_UPDATE(DWB_GAMUT_REMAP_COEF_FORMAT, DWB_GAMUT_REMAP_COEF_FORMAT, coef_format);

		if (regval == NULL \|\| select == CM_GAMUT_REMAP_MODE_BYPASS) {
		REG_SET(DWB_GAMUT_REMAP_MODE, 0,
		DWB_GAMUT_REMAP_MODE, 0);
		return;
		}

		switch (select) {
		case CM_GAMUT_REMAP_MODE_RAMA_COEFF:
		gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPA_C11_C12);
		gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPA_C33_C34);

		cm_helper_program_color_matrices(
		dwbc30->base.ctx,
		regval,
		&gam_regs);
		break;
		case CM_GAMUT_REMAP_MODE_RAMB_COEFF:
		gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPB_C11_C12);
		gam_regs.csc_c33_c34 = REG(DWB_GAMUT_REMAPB_C33_C34);

		cm_helper_program_color_matrices(
		dwbc30->base.ctx,
		regval,
		&gam_regs);
		break;
		case CM_GAMUT_REMAP_MODE_RESERVED:
		/* should never happen, bug */
		BREAK_TO_DEBUGGER();
		return;
		default:
		break;
		}

		REG_SET(DWB_GAMUT_REMAP_MODE, 0,
		DWB_GAMUT_REMAP_MODE, select);

		}

		void dwb3_set_gamut_remap(
		struct dwbc *dwbc,
		const struct dc_dwb_params *params)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);
		struct cm_grph_csc_adjustment adjust = params->csc_params;
		int i = 0;

		if (adjust.gamut_adjust_type != CM_GAMUT_ADJUST_TYPE_SW) {
		/* Bypass if type is bypass or hw */
		dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS);
		} else {
		struct fixed31_32 arr_matrix[12];
		uint16_t arr_reg_val[12];
		unsigned int current_mode;

		for (i = 0; i < 12; i++)
		arr_matrix[i] = adjust.temperature_matrix[i];

		convert_float_matrix(arr_reg_val, arr_matrix, 12);

		REG_GET(DWB_GAMUT_REMAP_MODE, DWB_GAMUT_REMAP_MODE_CURRENT, &current_mode);

		if (current_mode == CM_GAMUT_REMAP_MODE_RAMA_COEFF) {
		dwb3_program_gamut_remap(dwbc, arr_reg_val,
		adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMB_COEFF);
		} else {
		dwb3_program_gamut_remap(dwbc, arr_reg_val,
		adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_RAMA_COEFF);
		}
		}
		}

		void dwb3_program_hdr_mult(
		struct dwbc *dwbc,
		const struct dc_dwb_params *params)
		{
		struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

		REG_UPDATE(DWB_HDR_MULT_COEF, DWB_HDR_MULT_COEF, params->hdr_mult);
		}

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

+83 −0

Original line number	Diff line number	Diff line
		@@ -72,6 +72,67 @@ enum wbscl_coef_filter_type_sel {
		};


		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		enum dwb_boundary_mode {
		DWBSCL_BOUNDARY_MODE_EDGE = 0,
		DWBSCL_BOUNDARY_MODE_BLACK = 1
		};
		#endif

		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		enum dwb_output_csc_mode {
		DWB_OUTPUT_CSC_DISABLE = 0,
		DWB_OUTPUT_CSC_COEF_A = 1,
		DWB_OUTPUT_CSC_COEF_B = 2
		};

		enum dwb_ogam_lut_mode {
		DWB_OGAM_MODE_BYPASS,
		DWB_OGAM_RAMA_LUT,
		DWB_OGAM_RAMB_LUT
		};

		enum dwb_color_volume {
		DWB_SRGB_BT709 = 0, //SDR
		DWB_PQ = 1, //HDR
		DWB_HLG = 2, //HDR
		};

		enum dwb_color_space {
		DWB_SRGB = 0, //SDR
		DWB_BT709 = 1, //SDR
		DWB_BT2020 = 2, //HDR
		};

		struct dwb_efc_hdr_metadata {
		/display chromaticities and white point in units of 0.00001 /
		unsigned int chromaticity_green_x;
		unsigned int chromaticity_green_y;
		unsigned int chromaticity_blue_x;
		unsigned int chromaticity_blue_y;
		unsigned int chromaticity_red_x;
		unsigned int chromaticity_red_y;
		unsigned int chromaticity_white_point_x;
		unsigned int chromaticity_white_point_y;

		/in units of candelas per square meter /
		unsigned int min_luminance;
		unsigned int max_luminance;

		/in units of nits /
		unsigned int maximum_content_light_level;
		unsigned int maximum_frame_average_light_level;
		};

		struct dwb_efc_display_settings {
		unsigned int inputColorVolume;
		unsigned int inputColorSpace;
		unsigned int inputBitDepthMinus8;
		struct dwb_efc_hdr_metadata hdr_metadata;
		unsigned int dwbOutputBlack; // 0 - Normal, 1 - Output Black
		};

		#endif
		struct dwb_warmup_params {
		bool warmup_en; /* false: normal mode, true: enable pattern generator */
		bool warmup_mode; /* false: 420, true: 444 */
		@@ -148,6 +209,28 @@ struct dwbc_funcs {
		struct dwb_warmup_params *warmup_params);


		#if defined(CONFIG_DRM_AMD_DC_DCN3_0)

		void (*dwb_program_output_csc)(
		struct dwbc *dwbc,
		enum dc_color_space color_space,
		enum dwb_output_csc_mode mode);

		bool (*dwb_ogam_set_output_transfer_func)(
		struct dwbc *dwbc,
		const struct dc_transfer_func *in_transfer_func_dwb_ogam);

		void (*get_privacy_mask)(
		struct dwbc dwbc, uint32_t mask_id);

		void (*set_privacy_mask)(
		struct dwbc *dwbc, uint32_t mask_id);

		//TODO: merge with output_transfer_func?
		bool (*dwb_ogam_set_input_transfer_func)(
		struct dwbc *dwbc,
		const struct dc_transfer_func *in_transfer_func_dwb_ogam);
		#endif
		bool (*get_dwb_status)(
		struct dwbc *dwbc);
		void (*dwb_set_scaler)(

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