Commit 89522f0f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'at91-cleanup4_bis' of... 

Merge tag 'at91-cleanup4_bis' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/multiplatform

Pull "Fourth batch of cleanup for 4.1" from Nicolas Ferre:

- 1 issues revealed by the kbuild test robot fixed
- move of some functions and macros into relevant files to be able to
  streamline the at91 specific header afterwards

* tag 'at91-cleanup4_bis' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
  ARM: at91/pm: move AT91_MEMCTRL_* to pm.h
  ARM: at91/pm: move the standby functions to pm.c
  ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected
parents e8621d83 2e57dc08

arch/arm/mach-at91/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o 
obj-$(CONFIG_PM)		+= pm.o

obj-$(CONFIG_PM)		+= pm_suspend.o



ifeq ($(CONFIG_CPU_V7),y)

AFLAGS_pm_suspend.o := -march=armv7-a

endif

ifeq ($(CONFIG_PM_DEBUG),y)

CFLAGS_pm.o += -DDEBUG

endif

arch/arm/mach-at91/include/mach/at91_ramc.h

+0 −4
Original line number Diff line number Diff line
@@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[]; 
.extern at91_ramc_base

#endif



#define AT91_MEMCTRL_MC		0

#define AT91_MEMCTRL_SDRAMC	1

#define AT91_MEMCTRL_DDRSDR	2



#include <soc/at91/at91rm9200_sdramc.h>

#include <soc/at91/at91sam9_ddrsdr.h>

#include <soc/at91/at91sam9_sdramc.h>

arch/arm/mach-at91/pm.c

+89 −0
Original line number Diff line number Diff line
@@ -222,6 +222,95 @@ static void at91_pm_set_standby(void (*at91_standby)(void)) 
		at91_cpuidle_device.dev.platform_data = at91_standby;

}



/*

 * The AT91RM9200 goes into self-refresh mode with this command, and will

 * terminate self-refresh automatically on the next SDRAM access.

 *

 * Self-refresh mode is exited as soon as a memory access is made, but we don't

 * know for sure when that happens. However, we need to restore the low-power

 * mode if it was enabled before going idle. Restoring low-power mode while

 * still in self-refresh is "not recommended", but seems to work.

 */

static void at91rm9200_standby(void)

{

	u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);



	asm volatile(

		"b    1f\n\t"

		".align    5\n\t"

		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"

		"    str    %0, [%1, %2]\n\t"

		"    str    %3, [%1, %4]\n\t"

		"    mcr    p15, 0, %0, c7, c0, 4\n\t"

		"    str    %5, [%1, %2]"

		:

		: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),

		  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),

		  "r" (lpr));

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static void at91_ddr_standby(void)

{

	/* Those two values allow us to delay self-refresh activation

	 * to the maximum. */

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);

		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;

		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);

	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;

	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static void at91sam9_sdram_standby(void)

{

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);

		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;

		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);

	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;

	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);

}



static const struct of_device_id ramc_ids[] __initconst = {

	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },

	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },

arch/arm/mach-at91/pm.h

+4 −92
Original line number Diff line number Diff line
@@ -15,6 +15,10 @@ 


#include <mach/at91_ramc.h>



#define AT91_MEMCTRL_MC		0

#define AT91_MEMCTRL_SDRAMC	1

#define AT91_MEMCTRL_DDRSDR	2



#define	AT91_PM_MEMTYPE_MASK	0x0f



#define	AT91_PM_MODE_OFFSET	4
@@ -23,96 +27,4 @@ 


#define	AT91_PM_SLOW_CLOCK	0x01



/*

 * The AT91RM9200 goes into self-refresh mode with this command, and will

 * terminate self-refresh automatically on the next SDRAM access.

 *

 * Self-refresh mode is exited as soon as a memory access is made, but we don't

 * know for sure when that happens. However, we need to restore the low-power

 * mode if it was enabled before going idle. Restoring low-power mode while

 * still in self-refresh is "not recommended", but seems to work.

 */



#ifndef __ASSEMBLY__

static inline void at91rm9200_standby(void)

{

	u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);



	asm volatile(

		"b    1f\n\t"

		".align    5\n\t"

		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"

		"    str    %0, [%1, %2]\n\t"

		"    str    %3, [%1, %4]\n\t"

		"    mcr    p15, 0, %0, c7, c0, 4\n\t"

		"    str    %5, [%1, %2]"

		:

		: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),

		  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),

		  "r" (lpr));

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static inline void at91_ddr_standby(void)

{

	/* Those two values allow us to delay self-refresh activation

	 * to the maximum. */

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);

		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;

		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);

	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;

	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);

}



/* We manage both DDRAM/SDRAM controllers, we need more than one value to

 * remember.

 */

static inline void at91sam9_sdram_standby(void)

{

	u32 lpr0, lpr1 = 0;

	u32 saved_lpr0, saved_lpr1 = 0;



	if (at91_ramc_base[1]) {

		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);

		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;

		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;

	}



	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);

	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;

	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;



	/* self-refresh mode now */

	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);



	cpu_do_idle();



	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);

	if (at91_ramc_base[1])

		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);

}



#endif

#endif

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