Commit 894ca30c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'powerpc-4.11-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux 

Pull powerpc fixes from Michael Ellerman:
 "Some more powerpc fixes for 4.11:

  Headed to stable:

   - disable HFSCR[TM] if TM is not supported, fixes a potential host
     kernel crash triggered by a hostile guest, but only in
     configurations that no one uses

   - don't try to fix up misaligned load-with-reservation instructions

   - fix flush_(d|i)cache_range() called from modules on little endian
     kernels

   - add missing global TLB invalidate if cxl is active

   - fix missing preempt_disable() in crc32c-vpmsum

  And a fix for selftests build changes that went in this release:

   - selftests/powerpc: Fix standalone powerpc build

  Thanks to: Benjamin Herrenschmidt, Frederic Barrat, Oliver O'Halloran,
  Paul Mackerras"

* tag 'powerpc-4.11-7' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/crypto/crc32c-vpmsum: Fix missing preempt_disable()
  powerpc/mm: Add missing global TLB invalidate if cxl is active
  powerpc/64: Fix flush_(d|i)cache_range() called from modules
  powerpc: Don't try to fix up misaligned load-with-reservation instructions
  powerpc: Disable HFSCR[TM] if TM is not supported
  selftests/powerpc: Fix standalone powerpc build
parents cf01fb99 4749228f

arch/powerpc/crypto/crc32c-vpmsum_glue.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -33,10 +33,13 @@ static u32 crc32c_vpmsum(u32 crc, unsigned char const *p, size_t len) 
	}

	}





	if (len & ~VMX_ALIGN_MASK) {

	if (len & ~VMX_ALIGN_MASK) {

		preempt_disable();

		pagefault_disable();

		pagefault_disable();

		enable_kernel_altivec();

		enable_kernel_altivec();

		crc = __crc32c_vpmsum(crc, p, len & ~VMX_ALIGN_MASK);

		crc = __crc32c_vpmsum(crc, p, len & ~VMX_ALIGN_MASK);

		disable_kernel_altivec();

		pagefault_enable();

		pagefault_enable();

		preempt_enable();

	}

	}





	tail = len & VMX_ALIGN_MASK;

	tail = len & VMX_ALIGN_MASK;

arch/powerpc/kernel/align.c

+19 −8
Original line number Original line Diff line number Diff line
@@ -807,14 +807,25 @@ int fix_alignment(struct pt_regs *regs) 
	nb = aligninfo[instr].len;

	nb = aligninfo[instr].len;

	flags = aligninfo[instr].flags;

	flags = aligninfo[instr].flags;





	/* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */

	/*

	if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) {

	 * Handle some cases which give overlaps in the DSISR values.

	 */

	if (IS_XFORM(instruction)) {

		switch (get_xop(instruction)) {

		case 532:	/* ldbrx */

			nb = 8;

			nb = 8;

			flags = LD+SW;

			flags = LD+SW;

	} else if (IS_XFORM(instruction) &&

			break;

		   ((instruction >> 1) & 0x3ff) == 660) {

		case 660:	/* stdbrx */

			nb = 8;

			nb = 8;

			flags = ST+SW;

			flags = ST+SW;

			break;

		case 20:	/* lwarx */

		case 84:	/* ldarx */

		case 116:	/* lharx */

		case 276:	/* lqarx */

			return 0;	/* not emulated ever */

		}

	}

	}





	/* Byteswap little endian loads and stores */

	/* Byteswap little endian loads and stores */

arch/powerpc/kernel/misc_64.S

+2 −2
Original line number Original line Diff line number Diff line
@@ -67,7 +67,7 @@ PPC64_CACHES: 
 *   flush all bytes from start through stop-1 inclusive

 *   flush all bytes from start through stop-1 inclusive

 */

 */





_GLOBAL(flush_icache_range)

_GLOBAL_TOC(flush_icache_range)

BEGIN_FTR_SECTION

BEGIN_FTR_SECTION

	PURGE_PREFETCHED_INS

	PURGE_PREFETCHED_INS

	blr

	blr
@@ -120,7 +120,7 @@ EXPORT_SYMBOL(flush_icache_range) 
 *

 *

 *    flush all bytes from start to stop-1 inclusive

 *    flush all bytes from start to stop-1 inclusive

 */

 */

_GLOBAL(flush_dcache_range)

_GLOBAL_TOC(flush_dcache_range)





/*

/*

 * Flush the data cache to memory 

 * Flush the data cache to memory

arch/powerpc/kernel/setup_64.c

+9 −0
Original line number Original line Diff line number Diff line
@@ -236,6 +236,15 @@ static void cpu_ready_for_interrupts(void) 
		mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);

		mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);

	}

	}





	/*

	 * Fixup HFSCR:TM based on CPU features. The bit is set by our

	 * early asm init because at that point we haven't updated our

	 * CPU features from firmware and device-tree. Here we have,

	 * so let's do it.

	 */

	if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))

		mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);



	/* Set IR and DR in PACA MSR */

	/* Set IR and DR in PACA MSR */

	get_paca()->kernel_msr = MSR_KERNEL;

	get_paca()->kernel_msr = MSR_KERNEL;

}

}

arch/powerpc/mm/hash_native_64.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -638,6 +638,10 @@ static void native_flush_hash_range(unsigned long number, int local) 
	unsigned long psize = batch->psize;

	unsigned long psize = batch->psize;

	int ssize = batch->ssize;

	int ssize = batch->ssize;

	int i;

	int i;

	unsigned int use_local;



	use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&

		mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();





	local_irq_save(flags);

	local_irq_save(flags);
@@ -667,8 +671,7 @@ static void native_flush_hash_range(unsigned long number, int local) 
		} pte_iterate_hashed_end();

		} pte_iterate_hashed_end();

	}

	}





	if (mmu_has_feature(MMU_FTR_TLBIEL) &&

	if (use_local) {

	    mmu_psize_defs[psize].tlbiel && local) {

		asm volatile("ptesync":::"memory");

		asm volatile("ptesync":::"memory");

		for (i = 0; i < number; i++) {

		for (i = 0; i < number; i++) {

			vpn = batch->vpn[i];

			vpn = batch->vpn[i];

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