ARM: 7808/1: KVM: mm: Get rid of L_PTE_USER ref from PAGE_S2_DEVICE (8947c09d) · Commits · 戴 / test

THe L_PTE_USER actually has nothing to do with stage 2 mappings and the L_PTE_S2_RDWR value sets the readable bit, which was what L_PTE_USER was used for before proper handling of stage 2 memory defines. Changelog: [v3]: Drop call to kvm_set_s2pte_writable in mmu.c [v2]: Change default mappings to be r/w instead of r/o, as per Marc Zyngier's suggestion. Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:

Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/include/asm/pgtable.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -100,7 +100,7 @@ extern pgprot_t pgprot_s2_device;
		#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
		#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
		#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
		#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER \| L_PTE_S2_RDONLY)
		#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_S2_RDWR)

		#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT \| L_PTE_RDONLY \| L_PTE_XN \| L_PTE_NONE)
		#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_XN)

arch/arm/kvm/mmu.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -495,7 +495,6 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,

		for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
		pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
		kvm_set_s2pte_writable(&pte);

		ret = mmu_topup_memory_cache(&cache, 2, 2);
		if (ret)

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