Commit 8943835e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v4.3-rockchip32-soc2' of... 

Merge tag 'v4.3-rockchip32-soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc

Improve reliability of resume on rk3288 boards. For whatever
reason resuming from suspend worked sucessfully on the rk3288-evb
but not on other boards, like veyron-devices. Two problems seem
to have existed. For one the stabilization delays for pmic and
oscillator may have been to short and secondly the shallow
suspend seems to need GPIO wakups enabled. Normally this should
be covered by the more generic ARMINT wakeups already and
the reason for this is still investigated at Rockchip, but
meanwhile this makes boards actually resume.

* tag 'v4.3-rockchip32-soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

:
  ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend
  ARM: rockchip: set correct stabilization thresholds in suspend
  ARM: rockchip: rename osc_switch_to_32k variable

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents fb3c4426 9bb91ae9

arch/arm/mach-rockchip/pm.c

+27 −8
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ static bool rk3288_slp_disable_osc(void) 
static void rk3288_slp_mode_set(int level)

{

	u32 mode_set, mode_set1;

	bool osc_switch_to_32k = rk3288_slp_disable_osc();

	bool osc_disable = rk3288_slp_disable_osc();



	regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);

	regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
@@ -123,9 +123,6 @@ static void rk3288_slp_mode_set(int level) 
	regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,

		     rk3288_bootram_phy);



	regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,

		     PMU_ARMINT_WAKEUP_EN);



	mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |

		   BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |

		   BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
@@ -140,11 +137,27 @@ static void rk3288_slp_mode_set(int level) 
			    BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |

			    BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);



		if (osc_switch_to_32k)

		if (osc_disable)

			mode_set |= BIT(PMU_OSC_24M_DIS);



		mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |

			     BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);



		regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,

			     PMU_ARMINT_WAKEUP_EN);



		/*

		 * In deep suspend we use PMU_PMU_USE_LF to let the rk3288

		 * switch its main clock supply to the alternative 32kHz

		 * source. Therefore set 30ms on a 32kHz clock for pmic

		 * stabilization. Similar 30ms on 24MHz for the other

		 * mode below.

		 */

		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);



		/* only wait for stabilization, if we turned the osc off */

		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,

					 osc_disable ? 32 * 30 : 0);

	} else {

		/*

		 * arm off, logic normal
@@ -152,6 +165,15 @@ static void rk3288_slp_mode_set(int level) 
		 * wakeup will be error

		 */

		mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);



		regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,

			     PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN);



		/* 30ms on a 24MHz clock for pmic stabilization */

		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);



		/* oscillator is still running, so no need to wait */

		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);

	}



	regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
@@ -262,9 +284,6 @@ static int rk3288_suspend_init(struct device_node *np) 
	memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,

	       rk3288_bootram_sz);



	regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);

	regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);



	return 0;

}

arch/arm/mach-rockchip/pm.h

+1 −4
Original line number Diff line number Diff line
@@ -61,10 +61,7 @@ static inline void rockchip_suspend_init(void) 


/* PMU_WAKEUP_CFG1 bits */

#define PMU_ARMINT_WAKEUP_EN		BIT(0)



/* wait 30ms for OSC stable and 30ms for pmic stable */

#define OSC_STABL_CNT_THRESH	(32 * 30)

#define PMU_STABL_CNT_THRESH	(32 * 30)

#define PMU_GPIOINT_WAKEUP_EN		BIT(3)



enum rk3288_pwr_mode_con {

	PMU_PWR_MODE_EN = 0,

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