Unverified Commit 89434c3c authored Jan 03, 2018 by Geert Uytterhoeven Committed by Mark Brown Jan 03, 2018

spi: sh-msiof: Fix timeout failures for TX-only DMA transfers



When using RX (with or without TX), the DMA interrupt triggers
completion when the RX FIFO has been emptied, i.e. after the full
transfer has finished.

However, when using TX without RX, the DMA interrupt triggers completion
as soon as the DMA engine has filled the TX FIFO, i.e. before the full
transfer has finished.  Then sh_msiof_modify_ctr_wait() will spin until
the transfer has really finished and the TFSE bit is cleared, for at
most 1 ms.  For slow speeds and/or large transfers, this may cause
timeouts and transfer failures:

    spi_sh_msiof e6e10000.spi: failed to shut down hardware
    74x164 spi2.0: SPI transfer failed: -110
    spi_master spi2: failed to transfer one message from queue
    74x164 spi2.0: Failed writing: -110

Fix this by waiting explicitly until the TX FIFO has been emptied.

Based on a patch in the BSP by Hiromitsu Yamasaki.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>

parent 4fbd8d19

drivers/spi/spi-sh-msiof.c

+11 −1

Original line number	Diff line number	Diff line
		@@ -784,10 +784,20 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv p, const void tx,
		goto stop_dma;
		}

		/* wait for tx fifo to be emptied / rx fifo to be filled */
		/* wait for tx/rx DMA completion */
		ret = sh_msiof_wait_for_completion(p);
		if (ret)
		goto stop_reset;

		if (!rx) {
		reinit_completion(&p->done);
		sh_msiof_write(p, IER, IER_TEOFE);

		/* wait for tx fifo to be emptied */
		ret = sh_msiof_wait_for_completion(p);
		if (ret)
		goto stop_reset;
		}

		/* clear status bits */
		sh_msiof_reset_str(p);

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