Commit 89214f00 authored by Simon Arlott's avatar Simon Arlott Committed by Stephen Warren
Browse files

ARM: bcm2835: add interrupt controller driver 

The BCM2835 contains a custom interrupt controller, which supports 72
interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence the symbol naming in the
code.

This patch was extracted from git://github.com/lp0/linux.git

 branch
rpi-split as of 2012/09/08, and modified as follows:

* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
* Moved implementation to drivers/irchip/.
* Added devicetree documentation, and hence removed list of IRQs from
  bcm2835.dtsi.
* Changed shift in MAKE_HWIRQ() and HWIRQ_BANK() from 8 to 5 to reduce
  the size of the hwirq space, and pass the total size of the hwirq space
  to irq_domain_add_linear(), rather than just the number of valid hwirqs;
  the two are different due to the hwirq space being sparse.
* Added the interrupt controller DT node to the top-level of the DT,
  rather than nesting it inside a /axi node. Hence, changed the reg value
  since /axi had a ranges property. This seems simpler to me, but I'm not
  sure if everyone will like this change or not.
* Don't set struct irq_domain_ops.map = irq_domain_simple_map, hence
  removing the need to patch include/linux/irqdomain.h or
  kernel/irq/irqdomain.c.
* Simplified armctrl_of_init() using of_iomap().
* Removed unused IS_VALID_BANK()/IS_VALID_IRQ() macros.
* Renamed armctrl_handle_irq() to prevent possible symbol clashes.
* Made armctrl_of_init() static.
* Removed comment "Each bank is registered as a separate interrupt
  controller" since this is no longer true.
* Removed FSF address from license header.
* Added my name to copyright header.

Signed-off-by: default avatarChris Boot <bootc@bootc.net>
Signed-off-by: default avatarSimon Arlott <simon@fire.lp0.eu>
Signed-off-by: default avatarDom Cobley <popcornmix@gmail.com>
Signed-off-by: default avatarDom Cobley <dc4@broadcom.com>
Signed-off-by: default avatarStephen Warren <swarren@wwwdotorg.org>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ec9653b8

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

0 → 100644
+110 −0
Original line number Diff line number Diff line 
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller



The BCM2835 contains a custom top-level interrupt controller, which supports

72 interrupt sources using a 2-level register scheme. The interrupt

controller, or the HW block containing it, is referred to occasionally

as "armctrl" in the SoC documentation, hence naming of this binding.



Required properties:



- compatible : should be "brcm,bcm2835-armctrl-ic.txt"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 2.



  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic

  pending" register, or 1/2 respectively for interrupts in the "IRQ pending

  1/2" register.



  The 2nd cell contains the interrupt number within the bank. Valid values

  are 0..7 for bank 0, and 0..31 for bank 1.



The interrupt sources are as follows:



Bank 0:

0: ARM_TIMER

1: ARM_MAILBOX

2: ARM_DOORBELL_0

3: ARM_DOORBELL_1

4: VPU0_HALTED

5: VPU1_HALTED

6: ILLEGAL_TYPE0

7: ILLEGAL_TYPE1



Bank 1:

0: TIMER0

1: TIMER1

2: TIMER2

3: TIMER3

4: CODEC0

5: CODEC1

6: CODEC2

7: VC_JPEG

8: ISP

9: VC_USB

10: VC_3D

11: TRANSPOSER

12: MULTICORESYNC0

13: MULTICORESYNC1

14: MULTICORESYNC2

15: MULTICORESYNC3

16: DMA0

17: DMA1

18: VC_DMA2

19: VC_DMA3

20: DMA4

21: DMA5

22: DMA6

23: DMA7

24: DMA8

25: DMA9

26: DMA10

27: DMA11

28: DMA12

29: AUX

30: ARM

31: VPUDMA



Bank 2:

0: HOSTPORT

1: VIDEOSCALER

2: CCP2TX

3: SDC

4: DSI0

5: AVE

6: CAM0

7: CAM1

8: HDMI0

9: HDMI1

10: PIXELVALVE1

11: I2CSPISLV

12: DSI1

13: PWA0

14: PWA1

15: CPR

16: SMI

17: GPIO0

18: GPIO1

19: GPIO2

20: GPIO3

21: VC_I2C

22: VC_SPI

23: VC_I2SPCM

24: VC_SDIO

25: VC_UART

26: SLIMBUS

27: VEC

28: CPG

29: RNG

30: VC_ARASANSDIO

31: AVSPMON



Example:



intc: interrupt-controller {

	compatible = "brcm,bcm2835-armctrl-ic";

	reg = <0x7e00b200 0x200>;

	interrupt-controller;

	#interrupt-cells = <2>;

};

arch/arm/boot/dts/bcm2835.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
/ {

	compatible = "brcm,bcm2835";

	model = "BCM2835";

	interrupt-parent = <&intc>;



	chosen {

		bootargs = "earlyprintk";
@@ -13,5 +14,12 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x7e000000 0x20000000 0x02000000>;



		intc: interrupt-controller {

			compatible = "brcm,bcm2835-armctrl-ic";

			reg = <0x7e00b200 0x200>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};

	};

};

arch/arm/mach-bcm2835/bcm2835.c

+1 −9
Original line number Diff line number Diff line
@@ -13,12 +13,12 @@ 
 */



#include <linux/init.h>

#include <linux/irqchip/bcm2835.h>

#include <linux/of_platform.h>



#include <asm/mach/arch.h>

#include <asm/mach/map.h>

#include <asm/mach/time.h>

#include <asm/exception.h>



#include <mach/bcm2835_soc.h>
@@ -34,14 +34,6 @@ void __init bcm2835_map_io(void) 
	iotable_init(&io_map, 1);

}



void __init bcm2835_init_irq(void)

{

}



asmlinkage void __exception_irq_entry bcm2835_handle_irq(struct pt_regs *regs)

{

}



void __init bcm2835_init(void)

{

	int ret;

drivers/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -152,4 +152,6 @@ source "drivers/vme/Kconfig" 


source "drivers/pwm/Kconfig"



source "drivers/irqchip/Kconfig"



endmenu

drivers/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 
# Rewritten to use lists instead of if-statements.

#



obj-y				+= irqchip/



# GPIO must come after pinctrl as gpios may need to mux pins etc

obj-y				+= pinctrl/

obj-y				+= gpio/

CRA Git | Maintained and supported by SUSTech CRA and CCSE