Commit 88f59738 authored by Tomasz Figa's avatar Tomasz Figa Committed by Kukjin Kim
Browse files

ARM: SAMSUNG: Let platforms use the new watchdog reset driver 



This patch moves all platforms using the legacy watchdog reset helper
function to the new watchdog reset driver.

Signed-off-by: default avatarTomasz Figa <tomasz.figa@gmail.com>
Tested-by: default avatarSylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent a4658e57

arch/arm/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -729,6 +729,7 @@ config ARCH_S3C64XX 
	select SAMSUNG_CLKSRC

	select SAMSUNG_GPIOLIB_4BIT

	select SAMSUNG_IRQ_VIC_TIMER

	select SAMSUNG_WDT_RESET

	select USB_ARCH_HAS_OHCI

	help

	  Samsung S3C64XX series based systems
@@ -744,6 +745,7 @@ config ARCH_S5P64X0 
	select HAVE_S3C2410_WATCHDOG if WATCHDOG

	select HAVE_S3C_RTC if RTC_CLASS

	select NEED_MACH_GPIO_H

	select SAMSUNG_WDT_RESET

	help

	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,

	  SMDK6450.
@@ -760,6 +762,7 @@ config ARCH_S5PC100 
	select HAVE_S3C2410_WATCHDOG if WATCHDOG

	select HAVE_S3C_RTC if RTC_CLASS

	select NEED_MACH_GPIO_H

	select SAMSUNG_WDT_RESET

	help

	  Samsung S5PC100 series based systems

arch/arm/mach-s3c24xx/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ config CPU_S3C2410 
	select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX

	select S3C2410_PM if PM

	select SAMSUNG_HRT

	select SAMSUNG_WDT_RESET

	help

	  Support for S3C2410 and S3C2410A family from the S3C24XX line

	  of Samsung Mobile CPUs.
@@ -81,6 +82,7 @@ config CPU_S3C2442 
config CPU_S3C244X

	def_bool y

	depends on CPU_S3C2440 || CPU_S3C2442

	select SAMSUNG_WDT_RESET



config CPU_S3C2443

	bool "SAMSUNG S3C2443"

arch/arm/mach-s3c24xx/s3c2410.c

+2 −1
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ void __init s3c2410_init_clocks(int xtal) 
	s3c2410_baseclk_add();

	s3c24xx_register_clock(&s3c2410_armclk);

	clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));

	samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);

}



struct bus_type s3c2410_subsys = {
@@ -201,7 +202,7 @@ void s3c2410_restart(char mode, const char *cmd) 
		soft_restart(0);

	}



	arch_wdt_reset();

	samsung_wdt_reset();



	/* we'll take a jump through zero as a poor second */

	soft_restart(0);

arch/arm/mach-s3c24xx/s3c244x.c

+2 −1
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ void __init s3c244x_init_clocks(int xtal) 
	s3c24xx_register_baseclocks(xtal);

	s3c244x_setup_clocks();

	s3c2410_baseclk_add();

	samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);

}



/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
@@ -202,7 +203,7 @@ void s3c244x_restart(char mode, const char *cmd) 
	if (mode == 's')

		soft_restart(0);



	arch_wdt_reset();

	samsung_wdt_reset();



	/* we'll take a jump through zero as a poor second */

	soft_restart(0);

arch/arm/mach-s3c64xx/common.c

+7 −1
Original line number Diff line number Diff line
@@ -183,6 +183,12 @@ core_initcall(s3c64xx_dev_init); 


void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)

{

	/*

	 * FIXME: there is no better place to put this at the moment

	 * (samsung_wdt_reset_init needs clocks)

	 */

	samsung_wdt_reset_init(S3C_VA_WATCHDOG);



	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);



	/* initialise the pair of VICs */
@@ -378,7 +384,7 @@ arch_initcall(s3c64xx_init_irq_eint); 
void s3c64xx_restart(char mode, const char *cmd)

{

	if (mode != 's')

		arch_wdt_reset();

		samsung_wdt_reset();



	/* if all else fails, or mode was for soft, jump to 0 */

	soft_restart(0);

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