Commit 88efe190 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'dsa-mv88e6xxx-port-macros-cosmetics' 



Vivien Didelot says:

====================
net: dsa: mv88e6xxx: port macros cosmetics

This patch series brings no functional changes.

It prefixes all common port registers macros with MV88E6XXX_PORT.
If registers or some bits differs between switch models, a reference
model is chosen (e.g. MV88E6390_PORT_MAC_CTL_SPEED_10000.)

The register names are documented as found in the datasheets.

Avoid BIT() and shifts defines and prefer a better representation of the
Marvell switch registers with ordered, hexadecimal, 16-bit values.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents a1fa1a00 b8109594

drivers/net/dsa/mv88e6xxx/chip.c

+46 −44
Original line number Diff line number Diff line
@@ -828,11 +828,11 @@ static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 
	e->eee_enabled = !!(reg & 0x0200);

	e->tx_lpi_enabled = !!(reg & 0x0100);



	err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);

	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);

	if (err)

		goto out;



	e->eee_active = !!(reg & PORT_STATUS_EEE);

	e->eee_active = !!(reg & MV88E6352_PORT_STS_EEE);

out:

	mutex_unlock(&chip->reg_lock);
@@ -1213,8 +1213,8 @@ static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 
					 bool vlan_filtering)

{

	struct mv88e6xxx_chip *chip = ds->priv;

	u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :

		PORT_CONTROL_2_8021Q_DISABLED;

	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :

		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;

	int err;



	if (!chip->info->max_vid)
@@ -1729,14 +1729,14 @@ static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 
{

	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,

				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,

				       PORT_ETH_TYPE_DEFAULT);

				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);

}



static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)

{

	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,

				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,

				       PORT_ETH_TYPE_DEFAULT);

				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);

}



static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
@@ -1828,10 +1828,10 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
	 * If this is the upstream port for this switch, enable

	 * forwarding of unknown unicasts and multicasts.

	 */

	reg = PORT_CONTROL_IGMP_MLD_SNOOP |

		PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |

		PORT_CONTROL_STATE_FORWARDING;

	err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);

	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |

		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |

		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;

	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);

	if (err)

		return err;
@@ -1872,7 +1872,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
	}



	err = mv88e6xxx_port_set_8021q_mode(chip, port,

					    PORT_CONTROL_2_8021Q_DISABLED);

				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);

	if (err)

		return err;
@@ -1892,12 +1892,14 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
	if (dsa_is_cpu_port(ds, port))

		reg = 0;



	err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);

	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,

				   reg);

	if (err)

		return err;



	/* Egress rate control 2: disable egress rate control. */

	err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);

	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,

				   0x0000);

	if (err)

		return err;
@@ -1950,7 +1952,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 
	/* Default VLAN ID and priority: don't set a default VLAN

	 * ID, and set the default packet priority to zero.

	 */

	return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);

	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);

}



static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
@@ -2181,7 +2183,7 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 
		 * the mv88e6390 family model number instead.

		 */

		if (!(val & 0x3f0))

			val |= PORT_SWITCH_ID_PROD_NUM_6390;

			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;

	}



	return err ? err : val;
@@ -3162,7 +3164,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { 


static const struct mv88e6xxx_info mv88e6xxx_table[] = {

	[MV88E6085] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6085,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,

		.family = MV88E6XXX_FAMILY_6097,

		.name = "Marvell 88E6085",

		.num_databases = 4096,
@@ -3180,7 +3182,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6095] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6095,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,

		.family = MV88E6XXX_FAMILY_6095,

		.name = "Marvell 88E6095/88E6095F",

		.num_databases = 256,
@@ -3197,7 +3199,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6097] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6097,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,

		.family = MV88E6XXX_FAMILY_6097,

		.name = "Marvell 88E6097/88E6097F",

		.num_databases = 4096,
@@ -3215,7 +3217,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6123] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6123,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,

		.family = MV88E6XXX_FAMILY_6165,

		.name = "Marvell 88E6123",

		.num_databases = 4096,
@@ -3233,7 +3235,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6131] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6131,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,

		.family = MV88E6XXX_FAMILY_6185,

		.name = "Marvell 88E6131",

		.num_databases = 256,
@@ -3250,7 +3252,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6141] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6141,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,

		.family = MV88E6XXX_FAMILY_6341,

		.name = "Marvell 88E6341",

		.num_databases = 4096,
@@ -3267,7 +3269,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6161] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6161,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,

		.family = MV88E6XXX_FAMILY_6165,

		.name = "Marvell 88E6161",

		.num_databases = 4096,
@@ -3285,7 +3287,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6165] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6165,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,

		.family = MV88E6XXX_FAMILY_6165,

		.name = "Marvell 88E6165",

		.num_databases = 4096,
@@ -3303,7 +3305,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6171] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6171,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,

		.family = MV88E6XXX_FAMILY_6351,

		.name = "Marvell 88E6171",

		.num_databases = 4096,
@@ -3321,7 +3323,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6172] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6172,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,

		.family = MV88E6XXX_FAMILY_6352,

		.name = "Marvell 88E6172",

		.num_databases = 4096,
@@ -3339,7 +3341,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6175] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6175,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,

		.family = MV88E6XXX_FAMILY_6351,

		.name = "Marvell 88E6175",

		.num_databases = 4096,
@@ -3357,7 +3359,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6176] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6176,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,

		.family = MV88E6XXX_FAMILY_6352,

		.name = "Marvell 88E6176",

		.num_databases = 4096,
@@ -3375,7 +3377,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6185] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6185,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,

		.family = MV88E6XXX_FAMILY_6185,

		.name = "Marvell 88E6185",

		.num_databases = 256,
@@ -3392,7 +3394,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6190] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6190,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,

		.family = MV88E6XXX_FAMILY_6390,

		.name = "Marvell 88E6190",

		.num_databases = 4096,
@@ -3410,7 +3412,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6190X] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,

		.family = MV88E6XXX_FAMILY_6390,

		.name = "Marvell 88E6190X",

		.num_databases = 4096,
@@ -3428,7 +3430,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6191] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6191,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,

		.family = MV88E6XXX_FAMILY_6390,

		.name = "Marvell 88E6191",

		.num_databases = 4096,
@@ -3446,7 +3448,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6240] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6240,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,

		.family = MV88E6XXX_FAMILY_6352,

		.name = "Marvell 88E6240",

		.num_databases = 4096,
@@ -3464,7 +3466,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6290] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6290,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,

		.family = MV88E6XXX_FAMILY_6390,

		.name = "Marvell 88E6290",

		.num_databases = 4096,
@@ -3482,7 +3484,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6320] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6320,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,

		.family = MV88E6XXX_FAMILY_6320,

		.name = "Marvell 88E6320",

		.num_databases = 4096,
@@ -3500,7 +3502,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6321] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6321,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,

		.family = MV88E6XXX_FAMILY_6320,

		.name = "Marvell 88E6321",

		.num_databases = 4096,
@@ -3517,7 +3519,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6341] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6341,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,

		.family = MV88E6XXX_FAMILY_6341,

		.name = "Marvell 88E6341",

		.num_databases = 4096,
@@ -3534,7 +3536,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6350] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6350,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,

		.family = MV88E6XXX_FAMILY_6351,

		.name = "Marvell 88E6350",

		.num_databases = 4096,
@@ -3552,7 +3554,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6351] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6351,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,

		.family = MV88E6XXX_FAMILY_6351,

		.name = "Marvell 88E6351",

		.num_databases = 4096,
@@ -3570,7 +3572,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
	},



	[MV88E6352] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6352,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,

		.family = MV88E6XXX_FAMILY_6352,

		.name = "Marvell 88E6352",

		.num_databases = 4096,
@@ -3587,7 +3589,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.ops = &mv88e6352_ops,

	},

	[MV88E6390] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6390,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,

		.family = MV88E6XXX_FAMILY_6390,

		.name = "Marvell 88E6390",

		.num_databases = 4096,
@@ -3604,7 +3606,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.ops = &mv88e6390_ops,

	},

	[MV88E6390X] = {

		.prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,

		.family = MV88E6XXX_FAMILY_6390,

		.name = "Marvell 88E6390X",

		.num_databases = 4096,
@@ -3641,13 +3643,13 @@ static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 
	int err;



	mutex_lock(&chip->reg_lock);

	err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);

	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);

	mutex_unlock(&chip->reg_lock);

	if (err)

		return err;



	prod_num = (id & 0xfff0) >> 4;

	rev = id & 0x000f;

	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;

	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;



	info = mv88e6xxx_lookup_info(prod_num);

	if (!info)

drivers/net/dsa/mv88e6xxx/port.c

+178 −158

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/dsa/mv88e6xxx/port.h

+219 −160
Original line number Diff line number Diff line
@@ -17,166 +17,225 @@ 


#include "chip.h"



#define PORT_STATUS		0x00

#define PORT_STATUS_PAUSE_EN	BIT(15)

#define PORT_STATUS_MY_PAUSE	BIT(14)

#define PORT_STATUS_HD_FLOW	BIT(13)

#define PORT_STATUS_PHY_DETECT	BIT(12)

#define PORT_STATUS_LINK	BIT(11)

#define PORT_STATUS_DUPLEX	BIT(10)

#define PORT_STATUS_SPEED_MASK	0x0300

#define PORT_STATUS_SPEED_10	0x0000

#define PORT_STATUS_SPEED_100	0x0100

#define PORT_STATUS_SPEED_1000	0x0200

#define PORT_STATUS_EEE		BIT(6) /* 6352 */

#define PORT_STATUS_AM_DIS	BIT(6) /* 6165 */

#define PORT_STATUS_MGMII	BIT(6) /* 6185 */

#define PORT_STATUS_TX_PAUSED	BIT(5)

#define PORT_STATUS_FLOW_CTRL	BIT(4)

#define PORT_STATUS_CMODE_MASK	0x0f

#define PORT_STATUS_CMODE_100BASE_X	0x8

#define PORT_STATUS_CMODE_1000BASE_X	0x9

#define PORT_STATUS_CMODE_SGMII		0xa

#define PORT_STATUS_CMODE_2500BASEX	0xb

#define PORT_STATUS_CMODE_XAUI		0xc

#define PORT_STATUS_CMODE_RXAUI		0xd

#define PORT_PCS_CTRL		0x01

#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK	BIT(15)

#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK	BIT(14)

#define PORT_PCS_CTRL_FORCE_SPEED	BIT(13) /* 6390 */

#define PORT_PCS_CTRL_ALTSPEED		BIT(12) /* 6390 */

#define PORT_PCS_CTRL_200BASE		BIT(12) /* 6352 */

#define PORT_PCS_CTRL_FC		BIT(7)

#define PORT_PCS_CTRL_FORCE_FC		BIT(6)

#define PORT_PCS_CTRL_LINK_UP		BIT(5)

#define PORT_PCS_CTRL_FORCE_LINK	BIT(4)

#define PORT_PCS_CTRL_DUPLEX_FULL	BIT(3)

#define PORT_PCS_CTRL_FORCE_DUPLEX	BIT(2)

#define PORT_PCS_CTRL_SPEED_MASK	(0x03)

#define PORT_PCS_CTRL_SPEED_10		(0x00)

#define PORT_PCS_CTRL_SPEED_100		(0x01)

#define PORT_PCS_CTRL_SPEED_200		(0x02) /* 6065 and non Gb chips */

#define PORT_PCS_CTRL_SPEED_1000	(0x02)

#define PORT_PCS_CTRL_SPEED_10000	(0x03) /* 6390X */

#define PORT_PCS_CTRL_SPEED_UNFORCED	(0x03)

#define PORT_PAUSE_CTRL		0x02

#define PORT_FLOW_CTRL_LIMIT_IN		((0x00 << 8) | BIT(15))

#define PORT_FLOW_CTRL_LIMIT_OUT	((0x01 << 8) | BIT(15))

#define PORT_SWITCH_ID		0x03

#define PORT_SWITCH_ID_PROD_NUM_6085	0x04a

#define PORT_SWITCH_ID_PROD_NUM_6095	0x095

#define PORT_SWITCH_ID_PROD_NUM_6097	0x099

#define PORT_SWITCH_ID_PROD_NUM_6131	0x106

#define PORT_SWITCH_ID_PROD_NUM_6320	0x115

#define PORT_SWITCH_ID_PROD_NUM_6123	0x121

#define PORT_SWITCH_ID_PROD_NUM_6141	0x340

#define PORT_SWITCH_ID_PROD_NUM_6161	0x161

#define PORT_SWITCH_ID_PROD_NUM_6165	0x165

#define PORT_SWITCH_ID_PROD_NUM_6171	0x171

#define PORT_SWITCH_ID_PROD_NUM_6172	0x172

#define PORT_SWITCH_ID_PROD_NUM_6175	0x175

#define PORT_SWITCH_ID_PROD_NUM_6176	0x176

#define PORT_SWITCH_ID_PROD_NUM_6185	0x1a7

#define PORT_SWITCH_ID_PROD_NUM_6190	0x190

#define PORT_SWITCH_ID_PROD_NUM_6190X	0x0a0

#define PORT_SWITCH_ID_PROD_NUM_6191	0x191

#define PORT_SWITCH_ID_PROD_NUM_6240	0x240

#define PORT_SWITCH_ID_PROD_NUM_6290	0x290

#define PORT_SWITCH_ID_PROD_NUM_6321	0x310

#define PORT_SWITCH_ID_PROD_NUM_6341	0x341

#define PORT_SWITCH_ID_PROD_NUM_6352	0x352

#define PORT_SWITCH_ID_PROD_NUM_6350	0x371

#define PORT_SWITCH_ID_PROD_NUM_6351	0x375

#define PORT_SWITCH_ID_PROD_NUM_6390	0x390

#define PORT_SWITCH_ID_PROD_NUM_6390X	0x0a1

#define PORT_CONTROL		0x04

#define PORT_CONTROL_USE_CORE_TAG	BIT(15)

#define PORT_CONTROL_DROP_ON_LOCK	BIT(14)

#define PORT_CONTROL_EGRESS_UNMODIFIED	(0x0 << 12)

#define PORT_CONTROL_EGRESS_UNTAGGED	(0x1 << 12)

#define PORT_CONTROL_EGRESS_TAGGED	(0x2 << 12)

#define PORT_CONTROL_EGRESS_ADD_TAG	(0x3 << 12)

#define PORT_CONTROL_EGRESS_MASK	(0x3 << 12)

#define PORT_CONTROL_HEADER		BIT(11)

#define PORT_CONTROL_IGMP_MLD_SNOOP	BIT(10)

#define PORT_CONTROL_DOUBLE_TAG		BIT(9)

#define PORT_CONTROL_FRAME_MODE_NORMAL		(0x0 << 8)

#define PORT_CONTROL_FRAME_MODE_DSA		(0x1 << 8)

#define PORT_CONTROL_FRAME_MODE_PROVIDER	(0x2 << 8)

#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA	(0x3 << 8)

#define PORT_CONTROL_FRAME_MASK			(0x3 << 8)

#define PORT_CONTROL_DSA_TAG		BIT(8)

#define PORT_CONTROL_VLAN_TUNNEL	BIT(7)

#define PORT_CONTROL_TAG_IF_BOTH	BIT(6)

#define PORT_CONTROL_USE_IP		BIT(5)

#define PORT_CONTROL_USE_TAG		BIT(4)

#define PORT_CONTROL_FORWARD_UNKNOWN	BIT(2)

#define PORT_CONTROL_EGRESS_FLOODS_MASK			(0x3 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA	(0x0 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA	(0x1 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA	(0x2 << 2)

#define PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA	(0x3 << 2)

#define PORT_CONTROL_STATE_MASK		0x03

#define PORT_CONTROL_STATE_DISABLED	0x00

#define PORT_CONTROL_STATE_BLOCKING	0x01

#define PORT_CONTROL_STATE_LEARNING	0x02

#define PORT_CONTROL_STATE_FORWARDING	0x03

#define PORT_CONTROL_1		0x05

#define PORT_CONTROL_1_MESSAGE_PORT	BIT(15)

#define PORT_CONTROL_1_FID_11_4_MASK	(0xff << 0)

#define PORT_BASE_VLAN		0x06

#define PORT_BASE_VLAN_FID_3_0_MASK	(0xf << 12)

#define PORT_DEFAULT_VLAN	0x07

#define PORT_DEFAULT_VLAN_MASK	0xfff

#define PORT_CONTROL_2		0x08

#define PORT_CONTROL_2_IGNORE_FCS	BIT(15)

#define PORT_CONTROL_2_VTU_PRI_OVERRIDE	BIT(14)

#define PORT_CONTROL_2_SA_PRIO_OVERRIDE	BIT(13)

#define PORT_CONTROL_2_DA_PRIO_OVERRIDE	BIT(12)

#define PORT_CONTROL_2_JUMBO_MASK	(0x03 << 12)

#define PORT_CONTROL_2_JUMBO_1522	(0x00 << 12)

#define PORT_CONTROL_2_JUMBO_2048	(0x01 << 12)

#define PORT_CONTROL_2_JUMBO_10240	(0x02 << 12)

#define PORT_CONTROL_2_8021Q_MASK	(0x03 << 10)

#define PORT_CONTROL_2_8021Q_DISABLED	(0x00 << 10)

#define PORT_CONTROL_2_8021Q_FALLBACK	(0x01 << 10)

#define PORT_CONTROL_2_8021Q_CHECK	(0x02 << 10)

#define PORT_CONTROL_2_8021Q_SECURE	(0x03 << 10)

#define PORT_CONTROL_2_DISCARD_TAGGED	BIT(9)

#define PORT_CONTROL_2_DISCARD_UNTAGGED	BIT(8)

#define PORT_CONTROL_2_MAP_DA		BIT(7)

#define PORT_CONTROL_2_DEFAULT_FORWARD	BIT(6)

#define PORT_CONTROL_2_EGRESS_MONITOR	BIT(5)

#define PORT_CONTROL_2_INGRESS_MONITOR	BIT(4)

#define PORT_CONTROL_2_UPSTREAM_MASK	0x0f

#define PORT_RATE_CONTROL	0x09

#define PORT_RATE_CONTROL_2	0x0a

#define PORT_ASSOC_VECTOR	0x0b

#define PORT_ASSOC_VECTOR_HOLD_AT_1		BIT(15)

#define PORT_ASSOC_VECTOR_INT_AGE_OUT		BIT(14)

#define PORT_ASSOC_VECTOR_LOCKED_PORT		BIT(13)

#define PORT_ASSOC_VECTOR_IGNORE_WRONG		BIT(12)

#define PORT_ASSOC_VECTOR_REFRESH_LOCKED	BIT(11)

#define PORT_ATU_CONTROL	0x0c

#define PORT_PRI_OVERRIDE	0x0d

#define PORT_ETH_TYPE		0x0f

#define PORT_ETH_TYPE_DEFAULT	0x9100

#define PORT_IN_DISCARD_LO	0x10

#define PORT_IN_DISCARD_HI	0x11

#define PORT_IN_FILTERED	0x12

#define PORT_OUT_FILTERED	0x13

#define PORT_TAG_REGMAP_0123	0x18

#define PORT_TAG_REGMAP_4567	0x19

#define PORT_IEEE_PRIO_MAP_TABLE	0x18    /* 6390 */

#define PORT_IEEE_PRIO_MAP_TABLE_UPDATE		BIT(15)

#define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP		(0x0 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP	(0x1 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP	(0x2 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP		(0x3 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP	(0x5 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP	(0x6 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP	(0x7 << 12)

#define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT		9

/* Offset 0x00: Port Status Register */

#define MV88E6XXX_PORT_STS			0x00

#define MV88E6XXX_PORT_STS_PAUSE_EN		0x8000

#define MV88E6XXX_PORT_STS_MY_PAUSE		0x4000

#define MV88E6XXX_PORT_STS_HD_FLOW		0x2000

#define MV88E6XXX_PORT_STS_PHY_DETECT		0x1000

#define MV88E6XXX_PORT_STS_LINK			0x0800

#define MV88E6XXX_PORT_STS_DUPLEX		0x0400

#define MV88E6XXX_PORT_STS_SPEED_MASK		0x0300

#define MV88E6XXX_PORT_STS_SPEED_10		0x0000

#define MV88E6XXX_PORT_STS_SPEED_100		0x0100

#define MV88E6XXX_PORT_STS_SPEED_1000		0x0200

#define MV88E6352_PORT_STS_EEE			0x0040

#define MV88E6165_PORT_STS_AM_DIS		0x0040

#define MV88E6185_PORT_STS_MGMII		0x0040

#define MV88E6XXX_PORT_STS_TX_PAUSED		0x0020

#define MV88E6XXX_PORT_STS_FLOW_CTL		0x0010

#define MV88E6XXX_PORT_STS_CMODE_MASK		0x000f

#define MV88E6XXX_PORT_STS_CMODE_100BASE_X	0x0008

#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X	0x0009

#define MV88E6XXX_PORT_STS_CMODE_SGMII		0x000a

#define MV88E6XXX_PORT_STS_CMODE_2500BASEX	0x000b

#define MV88E6XXX_PORT_STS_CMODE_XAUI		0x000c

#define MV88E6XXX_PORT_STS_CMODE_RXAUI		0x000d



/* Offset 0x01: MAC (or PCS or Physical) Control Register */

#define MV88E6XXX_PORT_MAC_CTL				0x01

#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK	0x8000

#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK	0x4000

#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED		0x2000

#define MV88E6390_PORT_MAC_CTL_ALTSPEED			0x1000

#define MV88E6352_PORT_MAC_CTL_200BASE			0x1000

#define MV88E6XXX_PORT_MAC_CTL_FC			0x0080

#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC			0x0040

#define MV88E6XXX_PORT_MAC_CTL_LINK_UP			0x0020

#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK		0x0010

#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL		0x0008

#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX		0x0004

#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK		0x0003

#define MV88E6XXX_PORT_MAC_CTL_SPEED_10			0x0000

#define MV88E6XXX_PORT_MAC_CTL_SPEED_100		0x0001

#define MV88E6065_PORT_MAC_CTL_SPEED_200		0x0002

#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000		0x0002

#define MV88E6390_PORT_MAC_CTL_SPEED_10000		0x0003

#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED		0x0003



/* Offset 0x02: Jamming Control Register */

#define MV88E6097_PORT_JAM_CTL			0x02

#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK	0xff00

#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK	0x00ff



/* Offset 0x02: Flow Control Register */

#define MV88E6390_PORT_FLOW_CTL			0x02

#define MV88E6390_PORT_FLOW_CTL_UPDATE		0x8000

#define MV88E6390_PORT_FLOW_CTL_PTR_MASK	0x7f00

#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN	0x0000

#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT	0x0100

#define MV88E6390_PORT_FLOW_CTL_DATA_MASK	0x00ff



/* Offset 0x03: Switch Identifier Register */

#define MV88E6XXX_PORT_SWITCH_ID		0x03

#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK	0xfff0

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085	0x04a0

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095	0x0950

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097	0x0990

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X	0x0a00

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X	0x0a10

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131	0x1060

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320	0x1150

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123	0x1210

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161	0x1610

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165	0x1650

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171	0x1710

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172	0x1720

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175	0x1750

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176	0x1760

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190	0x1900

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191	0x1910

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185	0x1a70

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240	0x2400

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290	0x2900

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321	0x3100

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141	0x3400

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341	0x3410

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352	0x3520

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350	0x3710

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351	0x3750

#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390	0x3900

#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK	0x000f



/* Offset 0x04: Port Control Register */

#define MV88E6XXX_PORT_CTL0					0x04

#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG			0x8000

#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK			0x4000

#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK			0x3000

#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED		0x0000

#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED		0x1000

#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED			0x2000

#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA		0x3000

#define MV88E6XXX_PORT_CTL0_HEADER				0x0800

#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP			0x0400

#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG				0x0200

#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK			0x0300

#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL			0x0000

#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA			0x0100

#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER			0x0200

#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA		0x0300

#define MV88E6XXX_PORT_CTL0_DSA_TAG				0x0100

#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL				0x0080

#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH				0x0040

#define MV88E6185_PORT_CTL0_USE_IP				0x0020

#define MV88E6185_PORT_CTL0_USE_TAG				0x0010

#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN			0x0004

#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK			0x000c

#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA		0x0000

#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA	0x0004

#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA	0x0008

#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA	0x000c

#define MV88E6XXX_PORT_CTL0_STATE_MASK				0x0003

#define MV88E6XXX_PORT_CTL0_STATE_DISABLED			0x0000

#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING			0x0001

#define MV88E6XXX_PORT_CTL0_STATE_LEARNING			0x0002

#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING			0x0003



/* Offset 0x05: Port Control 1 */

#define MV88E6XXX_PORT_CTL1			0x05

#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT	0x8000

#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK	0x00ff



/* Offset 0x06: Port Based VLAN Map */

#define MV88E6XXX_PORT_BASE_VLAN		0x06

#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK	0xf000



/* Offset 0x07: Default Port VLAN ID & Priority */

#define MV88E6XXX_PORT_DEFAULT_VLAN		0x07

#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK	0x0fff



/* Offset 0x08: Port Control 2 Register */

#define MV88E6XXX_PORT_CTL2				0x08

#define MV88E6XXX_PORT_CTL2_IGNORE_FCS			0x8000

#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE		0x4000

#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE		0x2000

#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE		0x1000

#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK		0x3000

#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522		0x0000

#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048		0x1000

#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240		0x2000

#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK		0x0c00

#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED		0x0000

#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK		0x0400

#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK		0x0800

#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE		0x0c00

#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED		0x0200

#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED		0x0100

#define MV88E6XXX_PORT_CTL2_MAP_DA			0x0080

#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD		0x0040

#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR		0x0020

#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR		0x0010

#define MV88E6095_PORT_CTL2_CPU_PORT_MASK		0x000f



/* Offset 0x09: Egress Rate Control */

#define MV88E6XXX_PORT_EGRESS_RATE_CTL1		0x09



/* Offset 0x0A: Egress Rate Control 2 */

#define MV88E6XXX_PORT_EGRESS_RATE_CTL2		0x0a



/* Offset 0x0B: Port Association Vector */

#define MV88E6XXX_PORT_ASSOC_VECTOR			0x0b

#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1		0x8000

#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT		0x4000

#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT		0x2000

#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG	0x1000

#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED	0x0800



/* Offset 0x0C: Port ATU Control */

#define MV88E6XXX_PORT_ATU_CTL		0x0c



/* Offset 0x0D: Priority Override Register */

#define MV88E6XXX_PORT_PRI_OVERRIDE	0x0d



/* Offset 0x0E: Policy Control Register */

#define MV88E6XXX_PORT_POLICY_CTL	0x0e



/* Offset 0x0F: Port Special Ether Type */

#define MV88E6XXX_PORT_ETH_TYPE		0x0f

#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT	0x9100



/* Offset 0x10: InDiscards Low Counter */

#define MV88E6XXX_PORT_IN_DISCARD_LO	0x10



/* Offset 0x11: InDiscards High Counter */

#define MV88E6XXX_PORT_IN_DISCARD_HI	0x11



/* Offset 0x12: InFiltered Counter */

#define MV88E6XXX_PORT_IN_FILTERED	0x12



/* Offset 0x13: OutFiltered Counter */

#define MV88E6XXX_PORT_OUT_FILTERED	0x13



/* Offset 0x16: LED Control */

#define MV88E6XXX_PORT_LED_CONTROL	0x16



/* Offset 0x18: IEEE Priority Mapping Table */

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE			0x18

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE		0x8000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP		0x0000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP	0x1000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP	0x2000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP	0x3000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP	0x5000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP	0x6000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP	0x7000

#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT	9



/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */

#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123	0x18



/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */

#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567	0x19



int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,

			u16 *val);

drivers/net/dsa/mv88e6xxx/serdes.c

+19 −19
Original line number Diff line number Diff line
@@ -64,9 +64,9 @@ int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on) 
	if (err)

		return err;



	if ((cmode == PORT_STATUS_CMODE_100BASE_X) ||

	    (cmode == PORT_STATUS_CMODE_1000BASE_X) ||

	    (cmode == PORT_STATUS_CMODE_SGMII)) {

	if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASE_X) ||

	    (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X) ||

	    (cmode == MV88E6XXX_PORT_STS_CMODE_SGMII)) {

		err = mv88e6352_serdes_power_set(chip, on);

		if (err < 0)

			return err;
@@ -139,15 +139,15 @@ static int mv88e6390_serdes_lower(struct mv88e6xxx_chip *chip, u8 cmode, 
		return err;



	switch (cmode_donor) {

	case PORT_STATUS_CMODE_RXAUI:

	case MV88E6XXX_PORT_STS_CMODE_RXAUI:

		if (!rxaui)

			break;

		/* Fall through */

	case PORT_STATUS_CMODE_1000BASE_X:

	case PORT_STATUS_CMODE_SGMII:

	case PORT_STATUS_CMODE_2500BASEX:

		if (cmode == PORT_STATUS_CMODE_1000BASE_X ||

		    cmode == PORT_STATUS_CMODE_SGMII)

	case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:

	case MV88E6XXX_PORT_STS_CMODE_SGMII:

	case MV88E6XXX_PORT_STS_CMODE_2500BASEX:

		if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X ||

		    cmode == MV88E6XXX_PORT_STS_CMODE_SGMII)

			return	mv88e6390_serdes_sgmii(chip, lane, on);

	}

	return 0;
@@ -157,12 +157,12 @@ static int mv88e6390_serdes_port9(struct mv88e6xxx_chip *chip, u8 cmode, 
				  bool on)

{

	switch (cmode) {

	case PORT_STATUS_CMODE_1000BASE_X:

	case PORT_STATUS_CMODE_SGMII:

	case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:

	case MV88E6XXX_PORT_STS_CMODE_SGMII:

		return mv88e6390_serdes_sgmii(chip, MV88E6390_PORT9_LANE0, on);

	case PORT_STATUS_CMODE_XAUI:

	case PORT_STATUS_CMODE_RXAUI:

	case PORT_STATUS_CMODE_2500BASEX:

	case MV88E6XXX_PORT_STS_CMODE_XAUI:

	case MV88E6XXX_PORT_STS_CMODE_RXAUI:

	case MV88E6XXX_PORT_STS_CMODE_2500BASEX:

		return mv88e6390_serdes_10g(chip, MV88E6390_PORT9_LANE0, on);

	}
@@ -173,12 +173,12 @@ static int mv88e6390_serdes_port10(struct mv88e6xxx_chip *chip, u8 cmode, 
				   bool on)

{

	switch (cmode) {

	case PORT_STATUS_CMODE_SGMII:

	case MV88E6XXX_PORT_STS_CMODE_SGMII:

		return mv88e6390_serdes_sgmii(chip, MV88E6390_PORT10_LANE0, on);

	case PORT_STATUS_CMODE_XAUI:

	case PORT_STATUS_CMODE_RXAUI:

	case PORT_STATUS_CMODE_1000BASE_X:

	case PORT_STATUS_CMODE_2500BASEX:

	case MV88E6XXX_PORT_STS_CMODE_XAUI:

	case MV88E6XXX_PORT_STS_CMODE_RXAUI:

	case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:

	case MV88E6XXX_PORT_STS_CMODE_2500BASEX:

		return mv88e6390_serdes_10g(chip, MV88E6390_PORT10_LANE0, on);

	}

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