Unverified Commit 88eb404c authored by Kevin Li's avatar Kevin Li Committed by Mark Brown
Browse files

ASoC: brcm: Add DSL/PON SoC audio driver 



This patch adds Broadcom DSL/PON SoC audio driver
with Whistler I2S block. The SoC supported by this
patch are BCM63158B0,BCM63178 and BCM47622/6755

Signed-off-by: default avatarKevin Li <kevin-ke.li@broadcom.com>
Link: https://lore.kernel.org/r/20200312223242.2843-2-kevin-ke.li@broadcom.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 101247a3

sound/soc/bcm/Kconfig

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@@ -17,3 +17,12 @@ config SND_SOC_CYGNUS 
	  Cygnus chips (bcm958300, bcm958305, bcm911360)



	  If you don't know what to do here, say N.



config SND_BCM63XX_I2S_WHISTLER

	tristate "SoC Audio support for the Broadcom BCM63XX I2S module"

	select REGMAP_MMIO

	help

	  Say Y if you want to add support for ASoC audio on Broadcom

	  DSL/PON chips (bcm63158, bcm63178)



	  If you don't know what to do here, say N

sound/soc/bcm/Makefile

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@@ -9,3 +9,7 @@ snd-soc-cygnus-objs := cygnus-pcm.o cygnus-ssp.o 


obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-cygnus.o



# BCM63XX Platform Support

snd-soc-63xx-objs := bcm63xx-i2s-whistler.o bcm63xx-pcm-whistler.o



obj-$(CONFIG_SND_BCM63XX_I2S_WHISTLER) += snd-soc-63xx.o
 
 No newline at end of file

sound/soc/bcm/bcm63xx-i2s-whistler.c

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// SPDX-License-Identifier: GPL-2.0-or-later

// linux/sound/bcm/bcm63xx-i2s-whistler.c

// BCM63xx whistler i2s driver

// Copyright (c) 2020 Broadcom Corporation

// Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>



#include <linux/clk.h>

#include <linux/dma-mapping.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/regmap.h>

#include <sound/pcm_params.h>

#include <sound/soc.h>

#include "bcm63xx-i2s.h"



#define DRV_NAME "brcm-i2s"



static bool brcm_i2s_wr_reg(struct device *dev, unsigned int reg)

{

	switch (reg) {

	case I2S_TX_CFG ... I2S_TX_DESC_IFF_LEN:

	case I2S_TX_CFG_2 ... I2S_RX_DESC_IFF_LEN:

	case I2S_RX_CFG_2 ... I2S_REG_MAX:

		return true;

	default:

		return false;

	}

}



static bool brcm_i2s_rd_reg(struct device *dev, unsigned int reg)

{

	switch (reg) {

	case I2S_TX_CFG ... I2S_REG_MAX:

		return true;

	default:

		return false;

	}

}



static bool brcm_i2s_volatile_reg(struct device *dev, unsigned int reg)

{

	switch (reg) {

	case I2S_TX_CFG:

	case I2S_TX_IRQ_CTL:

	case I2S_TX_DESC_IFF_ADDR:

	case I2S_TX_DESC_IFF_LEN:

	case I2S_TX_DESC_OFF_ADDR:

	case I2S_TX_DESC_OFF_LEN:

	case I2S_TX_CFG_2:

	case I2S_RX_CFG:

	case I2S_RX_IRQ_CTL:

	case I2S_RX_DESC_OFF_ADDR:

	case I2S_RX_DESC_OFF_LEN:

	case I2S_RX_DESC_IFF_LEN:

	case I2S_RX_DESC_IFF_ADDR:

	case I2S_RX_CFG_2:

		return true;

	default:

		return false;

	}

}



static const struct regmap_config brcm_i2s_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = I2S_REG_MAX,

	.writeable_reg = brcm_i2s_wr_reg,

	.readable_reg = brcm_i2s_rd_reg,

	.volatile_reg = brcm_i2s_volatile_reg,

	.cache_type = REGCACHE_FLAT,

};



static int bcm63xx_i2s_hw_params(struct snd_pcm_substream *substream,

				 struct snd_pcm_hw_params *params,

				 struct snd_soc_dai *dai)

{

	int ret = 0;

	struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);



	ret = clk_set_rate(i2s_priv->i2s_clk, params_rate(params));

	if (ret < 0)

		dev_err(i2s_priv->dev,

			"Can't set sample rate, err: %d\n", ret);



	return ret;

}



static int bcm63xx_i2s_startup(struct snd_pcm_substream *substream,

			       struct snd_soc_dai *dai)

{

	unsigned int slavemode;

	struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);

	struct regmap *regmap_i2s = i2s_priv->regmap_i2s;



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {

		regmap_update_bits(regmap_i2s, I2S_TX_CFG,

				   I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |

				   I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE,

				   I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |

				   I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE);

		regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 0);

		regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 0);

		regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 1);



		/* TX and RX block each have an independent bit to indicate

		 * if it is generating the clock for the I2S bus. The bus

		 * clocks need to be generated from either the TX or RX block,

		 * but not both

		 */

		regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);

		if (slavemode & I2S_RX_SLAVE_MODE_MASK)

			regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,

					   I2S_TX_SLAVE_MODE_MASK,

					   I2S_TX_MASTER_MODE);

		else

			regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,

					   I2S_TX_SLAVE_MODE_MASK,

					   I2S_TX_SLAVE_MODE);

	} else {

		regmap_update_bits(regmap_i2s, I2S_RX_CFG,

				   I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |

				   I2S_RX_CLOCK_ENABLE,

				   I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |

				   I2S_RX_CLOCK_ENABLE);

		regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 0);

		regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 0);

		regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 1);



		regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);

		if (slavemode & I2S_TX_SLAVE_MODE_MASK)

			regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,

					   I2S_RX_SLAVE_MODE_MASK, 0);

		else

			regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,

					   I2S_RX_SLAVE_MODE_MASK,

					   I2S_RX_SLAVE_MODE);

	}

	return 0;

}



static void bcm63xx_i2s_shutdown(struct snd_pcm_substream *substream,

				struct snd_soc_dai *dai)

{

	unsigned int enabled, slavemode;

	struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);

	struct regmap *regmap_i2s = i2s_priv->regmap_i2s;



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {

		regmap_update_bits(regmap_i2s, I2S_TX_CFG,

				   I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |

				   I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE, 0);

		regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 1);

		regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 4);

		regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 4);



		regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);

		slavemode = slavemode & I2S_TX_SLAVE_MODE_MASK;

		if (!slavemode) {

			regmap_read(regmap_i2s, I2S_RX_CFG, &enabled);

			enabled = enabled & I2S_RX_ENABLE_MASK;

			if (enabled)

				regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,

						   I2S_RX_SLAVE_MODE_MASK,

						   I2S_RX_MASTER_MODE);

		}

		regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,

				   I2S_TX_SLAVE_MODE_MASK,

				   I2S_TX_SLAVE_MODE);

	} else {

		regmap_update_bits(regmap_i2s, I2S_RX_CFG,

				   I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |

				   I2S_RX_CLOCK_ENABLE, 0);

		regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 1);

		regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 4);

		regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 4);



		regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);

		slavemode = slavemode & I2S_RX_SLAVE_MODE_MASK;

		if (!slavemode) {

			regmap_read(regmap_i2s, I2S_TX_CFG, &enabled);

			enabled = enabled & I2S_TX_ENABLE_MASK;

			if (enabled)

				regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,

						   I2S_TX_SLAVE_MODE_MASK,

						   I2S_TX_MASTER_MODE);

		}



		regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,

				   I2S_RX_SLAVE_MODE_MASK, I2S_RX_SLAVE_MODE);

	}

}



static const struct snd_soc_dai_ops bcm63xx_i2s_dai_ops = {

	.startup = bcm63xx_i2s_startup,

	.shutdown = bcm63xx_i2s_shutdown,

	.hw_params = bcm63xx_i2s_hw_params,

};



static struct snd_soc_dai_driver bcm63xx_i2s_dai = {

	.name = DRV_NAME,

	.playback = {

		.channels_min = 2,

		.channels_max = 2,

		.rates = SNDRV_PCM_RATE_8000_192000,

		.formats = SNDRV_PCM_FMTBIT_S32_LE,

	},

	.capture = {

		.channels_min = 2,

		.channels_max = 2,

		.rates = SNDRV_PCM_RATE_8000_192000,

		.formats = SNDRV_PCM_FMTBIT_S32_LE,

	},

	.ops = &bcm63xx_i2s_dai_ops,

	.symmetric_rates = 1,

	.symmetric_channels = 1,

};



static const struct snd_soc_component_driver bcm63xx_i2s_component = {

	.name = "bcm63xx",

};



static int bcm63xx_i2s_dev_probe(struct platform_device *pdev)

{

	int ret = 0;

	void __iomem *regs;

	struct resource *r_mem, *region;

	struct bcm_i2s_priv *i2s_priv;

	struct regmap *regmap_i2s;

	struct clk *i2s_clk;



	i2s_priv = devm_kzalloc(&pdev->dev, sizeof(*i2s_priv), GFP_KERNEL);

	if (!i2s_priv)

		return -ENOMEM;



	i2s_clk = devm_clk_get(&pdev->dev, "i2sclk");

	if (IS_ERR(i2s_clk)) {

		dev_err(&pdev->dev, "%s: cannot get a brcm clock: %ld\n",

					__func__, PTR_ERR(i2s_clk));

		return PTR_ERR(i2s_clk);

	}



	r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!r_mem) {

		dev_err(&pdev->dev, "Unable to get register resource.\n");

		return -ENODEV;

	}



	region = devm_request_mem_region(&pdev->dev, r_mem->start,

					resource_size(r_mem), DRV_NAME);

	if (!region) {

		dev_err(&pdev->dev, "Memory region already claimed\n");

		return -EBUSY;

	}



	regs = devm_ioremap_resource(&pdev->dev, r_mem);

	if (IS_ERR(regs)) {

		ret = PTR_ERR(regs);

		return ret;

	}



	regmap_i2s = devm_regmap_init_mmio(&pdev->dev,

					regs, &brcm_i2s_regmap_config);

	if (IS_ERR(regmap_i2s))

		return PTR_ERR(regmap_i2s);



	regmap_update_bits(regmap_i2s, I2S_MISC_CFG,

			   I2S_PAD_LVL_LOOP_DIS_MASK,

			   I2S_PAD_LVL_LOOP_DIS_ENABLE);



	ret = devm_snd_soc_register_component(&pdev->dev,

					      &bcm63xx_i2s_component,

					      &bcm63xx_i2s_dai, 1);

	if (ret) {

		dev_err(&pdev->dev, "failed to register the dai\n");

		return ret;

	}



	i2s_priv->dev = &pdev->dev;

	i2s_priv->i2s_clk = i2s_clk;

	i2s_priv->regmap_i2s = regmap_i2s;

	dev_set_drvdata(&pdev->dev, i2s_priv);



	ret = bcm63xx_soc_platform_probe(pdev, i2s_priv);

	if (ret)

		dev_err(&pdev->dev, "failed to register the pcm\n");



	return ret;

}



static int bcm63xx_i2s_dev_remove(struct platform_device *pdev)

{

	bcm63xx_soc_platform_remove(pdev);

	return 0;

}



#ifdef CONFIG_OF

static const struct of_device_id snd_soc_bcm_audio_match[] = {

	{.compatible = "brcm,bcm63xx-i2s"},

	{ }

};

#endif



static struct platform_driver bcm63xx_i2s_driver = {

	.driver = {

		.name = DRV_NAME,

		.of_match_table = of_match_ptr(snd_soc_bcm_audio_match),

	},

	.probe = bcm63xx_i2s_dev_probe,

	.remove = bcm63xx_i2s_dev_remove,

};



module_platform_driver(bcm63xx_i2s_driver);



MODULE_AUTHOR("Kevin,Li <kevin-ke.li@broadcom.com>");

MODULE_DESCRIPTION("Broadcom DSL XPON ASOC I2S Interface");

MODULE_LICENSE("GPL v2");

sound/soc/bcm/bcm63xx-i2s.h

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// SPDX-License-Identifier: GPL-2.0-or-later

// linux/sound/soc/bcm/bcm63xx-i2s.h

// Copyright (c) 2020 Broadcom Corporation

// Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>



#ifndef __BCM63XX_I2S_H

#define __BCM63XX_I2S_H



#define I2S_DESC_FIFO_DEPTH		8

#define I2S_MISC_CFG			(0x003C)

#define I2S_PAD_LVL_LOOP_DIS_MASK	(1 << 2)

#define I2S_PAD_LVL_LOOP_DIS_ENABLE	I2S_PAD_LVL_LOOP_DIS_MASK



#define I2S_TX_ENABLE_MASK		(1 << 31)

#define I2S_TX_ENABLE			I2S_TX_ENABLE_MASK

#define I2S_TX_OUT_R			(1 << 19)

#define I2S_TX_DATA_ALIGNMENT		(1 << 2)

#define I2S_TX_DATA_ENABLE		(1 << 1)

#define I2S_TX_CLOCK_ENABLE		(1 << 0)



#define I2S_TX_DESC_OFF_LEVEL_SHIFT	12

#define I2S_TX_DESC_OFF_LEVEL_MASK	(0x0F << I2S_TX_DESC_OFF_LEVEL_SHIFT)

#define I2S_TX_DESC_IFF_LEVEL_SHIFT	8

#define I2S_TX_DESC_IFF_LEVEL_MASK	(0x0F << I2S_TX_DESC_IFF_LEVEL_SHIFT)

#define I2S_TX_DESC_OFF_INTR_EN_MSK	(1 << 1)

#define I2S_TX_DESC_OFF_INTR_EN	I2S_TX_DESC_OFF_INTR_EN_MSK



#define I2S_TX_CFG			(0x0000)

#define I2S_TX_IRQ_CTL			(0x0004)

#define I2S_TX_IRQ_EN			(0x0008)

#define I2S_TX_IRQ_IFF_THLD		(0x000c)

#define I2S_TX_IRQ_OFF_THLD		(0x0010)

#define I2S_TX_DESC_IFF_ADDR		(0x0014)

#define I2S_TX_DESC_IFF_LEN		(0x0018)

#define I2S_TX_DESC_OFF_ADDR		(0x001C)

#define I2S_TX_DESC_OFF_LEN		(0x0020)

#define I2S_TX_CFG_2			(0x0024)

#define I2S_TX_SLAVE_MODE_SHIFT	13

#define I2S_TX_SLAVE_MODE_MASK		(1 << I2S_TX_SLAVE_MODE_SHIFT)

#define I2S_TX_SLAVE_MODE		I2S_TX_SLAVE_MODE_MASK

#define I2S_TX_MASTER_MODE		0

#define I2S_TX_INTR_MASK		0x0F



#define I2S_RX_ENABLE_MASK		(1 << 31)

#define I2S_RX_ENABLE			I2S_RX_ENABLE_MASK

#define I2S_RX_IN_R			(1 << 19)

#define I2S_RX_DATA_ALIGNMENT		(1 << 2)

#define I2S_RX_CLOCK_ENABLE		(1 << 0)



#define I2S_RX_DESC_OFF_LEVEL_SHIFT	12

#define I2S_RX_DESC_OFF_LEVEL_MASK	(0x0F << I2S_RX_DESC_OFF_LEVEL_SHIFT)

#define I2S_RX_DESC_IFF_LEVEL_SHIFT	8

#define I2S_RX_DESC_IFF_LEVEL_MASK	(0x0F << I2S_RX_DESC_IFF_LEVEL_SHIFT)

#define I2S_RX_DESC_OFF_INTR_EN_MSK	(1 << 1)

#define I2S_RX_DESC_OFF_INTR_EN	I2S_RX_DESC_OFF_INTR_EN_MSK



#define I2S_RX_CFG			(0x0040) /* 20c0 */

#define I2S_RX_IRQ_CTL			(0x0044)

#define I2S_RX_IRQ_EN			(0x0048)

#define I2S_RX_IRQ_IFF_THLD		(0x004C)

#define I2S_RX_IRQ_OFF_THLD		(0x0050)

#define I2S_RX_DESC_IFF_ADDR		(0x0054)

#define I2S_RX_DESC_IFF_LEN		(0x0058)

#define I2S_RX_DESC_OFF_ADDR		(0x005C)

#define I2S_RX_DESC_OFF_LEN		(0x0060)

#define I2S_RX_CFG_2			(0x0064)

#define I2S_RX_SLAVE_MODE_SHIFT	13

#define I2S_RX_SLAVE_MODE_MASK		(1 << I2S_RX_SLAVE_MODE_SHIFT)

#define I2S_RX_SLAVE_MODE		I2S_RX_SLAVE_MODE_MASK

#define I2S_RX_MASTER_MODE		0

#define I2S_RX_INTR_MASK		0x0F



#define I2S_REG_MAX			0x007C



struct bcm_i2s_priv {

	struct device *dev;

	struct resource *r_irq;

	struct regmap *regmap_i2s;

	struct clk *i2s_clk;

	struct snd_pcm_substream	*play_substream;

	struct snd_pcm_substream	*capture_substream;

	struct i2s_dma_desc *play_dma_desc;

	struct i2s_dma_desc *capture_dma_desc;

};



extern int bcm63xx_soc_platform_probe(struct platform_device *pdev,

				      struct bcm_i2s_priv *i2s_priv);

extern int bcm63xx_soc_platform_remove(struct platform_device *pdev);



#endif

sound/soc/bcm/bcm63xx-pcm-whistler.c

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