clk: meson: g12a: add MIPI DSI Host Pixel Clock (88b9ae60) · Commits · 戴 / test

drivers/clk/meson/g12a.c

+74 −0

Original line number	Diff line number	Diff line
		@@ -3658,6 +3658,68 @@ static struct clk_regmap g12a_hdmi_tx = {
		},
		};

		/* MIPI DSI Host Clocks */

		static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
		&g12a_vid_pll.hw,
		&g12a_gp0_pll.hw,
		&g12a_hifi_pll.hw,
		&g12a_mpll1.hw,
		&g12a_fclk_div2.hw,
		&g12a_fclk_div2p5.hw,
		&g12a_fclk_div3.hw,
		&g12a_fclk_div7.hw,
		};

		static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
		.data = &(struct clk_regmap_mux_data){
		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
		.mask = 0x7,
		.shift = 12,
		.flags = CLK_MUX_ROUND_CLOSEST,
		},
		.hw.init = &(struct clk_init_data){
		.name = "mipi_dsi_pxclk_sel",
		.ops = &clk_regmap_mux_ops,
		.parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
		.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
		.flags = CLK_SET_RATE_NO_REPARENT,
		},
		};

		static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
		.data = &(struct clk_regmap_div_data){
		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
		.shift = 0,
		.width = 7,
		},
		.hw.init = &(struct clk_init_data){
		.name = "mipi_dsi_pxclk_div",
		.ops = &clk_regmap_divider_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&g12a_mipi_dsi_pxclk_sel.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		static struct clk_regmap g12a_mipi_dsi_pxclk = {
		.data = &(struct clk_regmap_gate_data){
		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
		.bit_idx = 8,
		},
		.hw.init = &(struct clk_init_data) {
		.name = "mipi_dsi_pxclk",
		.ops = &clk_regmap_gate_ops,
		.parent_hws = (const struct clk_hw *[]) {
		&g12a_mipi_dsi_pxclk_div.hw
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		},
		};

		/* HDMI Clocks */

		static const struct clk_parent_data g12a_hdmi_parent_data[] = {
		@@ -4403,6 +4465,9 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
		[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
		[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
		[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
		[CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
		[CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
		[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
		[NR_CLKS] = NULL,
		},
		.num = NR_CLKS,
		@@ -4658,6 +4723,9 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
		[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
		[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
		[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
		[CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
		[CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
		[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
		[NR_CLKS] = NULL,
		},
		.num = NR_CLKS,
		@@ -4904,6 +4972,9 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
		[CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
		[CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
		[CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
		[CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
		[CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
		[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
		[NR_CLKS] = NULL,
		},
		.num = NR_CLKS,
		@@ -5151,6 +5222,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
		&sm1_nna_core_clk_sel,
		&sm1_nna_core_clk_div,
		&sm1_nna_core_clk,
		&g12a_mipi_dsi_pxclk_sel,
		&g12a_mipi_dsi_pxclk_div,
		&g12a_mipi_dsi_pxclk,
		};

		static const struct reg_sequence g12a_init_regs[] = {

drivers/clk/meson/g12a.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -264,8 +264,9 @@
		#define CLKID_NNA_AXI_CLK_DIV 263
		#define CLKID_NNA_CORE_CLK_SEL 265
		#define CLKID_NNA_CORE_CLK_DIV 266
		#define CLKID_MIPI_DSI_PXCLK_DIV 268

		#define NR_CLKS 268
		#define NR_CLKS 271

		/* include the CLKIDs that have been made part of the DT binding */
		#include <dt-bindings/clock/g12a-clkc.h>

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