Commit 88b4bd70 authored Dec 26, 2013 by Andrew Bresticker Committed by Peter De Schrijver Feb 17, 2014

clk: tegra: cclk_lp has a pllx/2 divider



When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2.  Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>

parent 20e7c323

drivers/clk/tegra/clk-tegra-super-gen4.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -120,7 +120,7 @@ void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
		ARRAY_SIZE(cclk_lp_parents),
		CLK_SET_RATE_PARENT,
		clk_base + CCLKLP_BURST_POLICY,
		0, 4, 8, 9, NULL);
		TEGRA_DIVIDER_2, 4, 8, 9, NULL);
		*dt_clk = clk;
		}

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