arm64: capabilities: Rework EL2 vector hardening entry (8892b718) · Commits · 戴 / test

Since ("arm64: capabilities: Clean up midr range helpers"), capabilities must be represented with a single entry. If multiple CPU types can use the same capability, then they need to be enumerated in a list. The EL2 hardening stuff (which affects both A57 and A72) managed to escape the conversion in the above patch thanks to the 4.17 merge window. Let's fix it now. Signed-off-by:

Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:

Will Deacon <will.deacon@arm.com>

arch/arm64/kernel/cpu_errata.c

+11 −9

Original line number	Diff line number	Diff line
		@@ -324,8 +324,14 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = {

		#endif

		#ifndef ERRATA_MIDR_ALL_VERSIONS
		#define ERRATA_MIDR_ALL_VERSIONS(x) MIDR_ALL_VERSIONS(x)
		#ifdef CONFIG_HARDEN_EL2_VECTORS

		static const struct midr_range arm64_harden_el2_vectors[] = {
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
		{},
		};

		#endif

		const struct arm64_cpu_capabilities arm64_errata[] = {
		@@ -478,14 +484,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
		#endif
		#ifdef CONFIG_HARDEN_EL2_VECTORS
		{
		.desc = "Cortex-A57 EL2 vector hardening",
		.desc = "EL2 vector hardening",
		.capability = ARM64_HARDEN_EL2_VECTORS,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
		},
		{
		.desc = "Cortex-A72 EL2 vector hardening",
		.capability = ARM64_HARDEN_EL2_VECTORS,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
		ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
		},
		#endif
		{

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