Commit 8855e14d authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt-for-v4.12' of... 

Merge tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.12

Cleanup:
* Drop superfluous status update for frequency override on various boards
* Always use status "okay" to enable devices on porger board
* Add INTC-SYS clock to device tree of various SoCs
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
* Remove unit-address and reg from integrated cache on various SoCs
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs

Enhancements:
* Add watchdog timer to r7s72100 SoC
* Update sdhi clock bindings on r7s72100 SoC

* tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

: (31 commits)
  ARM: dts: silk: Drop superfluous status update for frequency override
  ARM: dts: alt: Drop superfluous status update for frequency override
  ARM: dts: gose: Drop superfluous status update for frequency override
  ARM: dts: porter: Drop superfluous status update for frequency override
  ARM: dts: koelsch: Drop superfluous status updates for frequency overrides
  ARM: dts: lager: Drop superfluous status update for frequency override
  ARM: dts: marzen: Drop superfluous status update for frequency override
  ARM: dts: bockw: Drop superfluous status update for frequency override
  ARM: dts: porter: Always use status "okay" to enable devices
  ARM: dts: r8a7793: Add INTC-SYS clock to device tree
  ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC
  ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC
  ARM: dts: r8a7794: Add INTC-SYS clock to device tree
  ARM: dts: r8a7792: Add INTC-SYS clock to device tree
  ARM: dts: r8a7791: Add INTC-SYS clock to device tree
  ARM: dts: r8a7790: Add INTC-SYS clock to device tree
  ARM: dts: r8a73a4: Add INTC-SYS clock to device tree
  ARM: dts: r7s72100: Add watchdog timer
  ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC
  ARM: dts: r8a7794: Remove unit-address and reg from integrated cache
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c2a736b6 d01ff189

arch/arm/boot/dts/Makefile

+19 −19
Original line number Diff line number Diff line
@@ -679,6 +679,25 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \ 
	arm-realview-eb-a9mp-bbrevd.dtb \

	arm-realview-pba8.dtb \

	arm-realview-pbx-a9.dtb

dtb-$(CONFIG_ARCH_RENESAS) += \

	emev2-kzm9d.dtb \

	r7s72100-genmai.dtb \

	r7s72100-rskrza1.dtb \

	r8a73a4-ape6evm.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7743-sk-rzg1m.dtb \

	r8a7745-sk-rzg1e.dtb \

	r8a7778-bockw.dtb \

	r8a7779-marzen.dtb \

	r8a7790-lager.dtb \

	r8a7791-koelsch.dtb \

	r8a7791-porter.dtb \

	r8a7792-blanche.dtb \

	r8a7792-wheat.dtb \

	r8a7793-gose.dtb \

	r8a7794-alt.dtb \

	r8a7794-silk.dtb \

	sh73a0-kzm9g.dtb

dtb-$(CONFIG_ARCH_ROCKCHIP) += \

	rk1108-evb.dtb \

	rk3036-evb.dtb \
@@ -719,25 +738,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ 
	s5pv210-smdkc110.dtb \

	s5pv210-smdkv210.dtb \

	s5pv210-torbreck.dtb

dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \

	emev2-kzm9d.dtb \

	r7s72100-genmai.dtb \

	r7s72100-rskrza1.dtb \

	r8a73a4-ape6evm.dtb \

	r8a7740-armadillo800eva.dtb \

	r8a7743-sk-rzg1m.dtb \

	r8a7745-sk-rzg1e.dtb \

	r8a7778-bockw.dtb \

	r8a7779-marzen.dtb \

	r8a7790-lager.dtb \

	r8a7791-koelsch.dtb \

	r8a7791-porter.dtb \

	r8a7792-blanche.dtb \

	r8a7792-wheat.dtb \

	r8a7793-gose.dtb \

	r8a7794-alt.dtb \

	r8a7794-silk.dtb \

	sh73a0-kzm9g.dtb

dtb-$(CONFIG_ARCH_SOCFPGA) += \

	socfpga_arria5_socdk.dtb \

	socfpga_arria10_socdk_nand.dtb \

arch/arm/boot/dts/r7s72100.dtsi

+19 −5
Original line number Diff line number Diff line
@@ -162,9 +162,12 @@ 
			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0444 4>;

			clocks = <&p1_clk>, <&p1_clk>;

			clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;

			clock-output-names = "sdhi1", "sdhi0";

			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;

			clock-indices = <

				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01

				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11

			>;

			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";

		};

	};
@@ -368,6 +371,13 @@ 
			<0xe8202000 0x1000>;

	};



	wdt: watchdog@fcfe0000 {

		compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";

		reg = <0xfcfe0000 0x6>;

		interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;

		clocks = <&p0_clk>;

	};



	i2c0: i2c@fcfee000 {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -488,7 +498,9 @@ 
			      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;



		clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;

		clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,

			 <&mstp12_clks R7S72100_CLK_SDHI01>;

		clock-names = "core", "cd";

		cap-sd-highspeed;

		cap-sdio-irq;

		status = "disabled";
@@ -501,7 +513,9 @@ 
			      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH

			      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;



		clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;

		clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,

			 <&mstp12_clks R7S72100_CLK_SDHI11>;

		clock-names = "core", "cd";

		cap-sd-highspeed;

		cap-sdio-irq;

		status = "disabled";

arch/arm/boot/dts/r8a73a4.dtsi

+11 −8
Original line number Diff line number Diff line
@@ -32,18 +32,16 @@ 
			next-level-cache = <&L2_CA15>;

		};



		L2_CA15: cache-controller@0 {

		L2_CA15: cache-controller-0 {

			compatible = "cache";

			reg = <0>;

			clocks = <&cpg_clocks R8A73A4_CLK_Z>;

			power-domains = <&pd_a3sm>;

			cache-unified;

			cache-level = <2>;

		};



		L2_CA7: cache-controller@100 {

		L2_CA7: cache-controller-1 {

			compatible = "cache";

			reg = <0x100>;

			clocks = <&cpg_clocks R8A73A4_CLK_Z2>;

			power-domains = <&pd_a3km>;

			cache-unified;
@@ -469,6 +467,9 @@ 
			<0 0xf1004000 0 0x2000>,

			<0 0xf1006000 0 0x2000>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;

		clock-names = "clk";

		power-domains = <&pd_c4>;

	};



	bsc: bus@fec10000 {
@@ -727,16 +728,18 @@ 
		mstp4_clks: mstp4_clks@e6150140 {

			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;

			clocks = <&main_div2_clk>, <&main_div2_clk>,

			clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,

				 <&main_div2_clk>,

				 <&cpg_clocks R8A73A4_CLK_HP>,

				 <&cpg_clocks R8A73A4_CLK_HP>;

			#clock-cells = <1>;

			clock-indices = <

				R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5

				R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3

				R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS

				R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4

				R8A73A4_CLK_IIC3

			>;

			clock-output-names =

				"irqc", "iic5", "iic4", "iic3";

				"irqc", "intc-sys", "iic5", "iic4", "iic3";

		};

		mstp5_clks: mstp5_clks@e6150144 {

			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";

arch/arm/boot/dts/r8a7743.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -32,9 +32,8 @@ 
			next-level-cache = <&L2_CA15>;

		};



		L2_CA15: cache-controller@0 {

		L2_CA15: cache-controller-0 {

			compatible = "cache";

			reg = <0>;

			cache-unified;

			cache-level = <2>;

			power-domains = <&sysc R8A7743_PD_CA15_SCU>;

arch/arm/boot/dts/r8a7745.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -32,9 +32,8 @@ 
			next-level-cache = <&L2_CA7>;

		};



		L2_CA7: cache-controller@0 {

		L2_CA7: cache-controller-0 {

			compatible = "cache";

			reg = <0>;

			cache-unified;

			cache-level = <2>;

			power-domains = <&sysc R8A7745_PD_CA7_SCU>;

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