Commit 8842a9e2 authored by Shawn Guo's avatar Shawn Guo
Browse files

ARM: imx: enable SPARSE_IRQ for imx platform 



As all irqchips on imx have been changed to allocate their irq_descs,
and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
now it's time to select SPARSE_IRQ for imx/mxc.

The SPARSE_IRQ support forces irqs allocation starting from 16.  All
those static irq number definition for SoCs need to shift 16 to keep
non-DT boot works.

With all those static IRQ number and start definitions removed from
mach/irqs.h, the header becomes just a container of a couple of
mach-imx specific irq/fiq calls.  Since mach/irqs.h is not included
by asm/irq.h now, the users of mxc_set_irq_fiq needs to explicitly
include mach/irqs.h themselves.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent bc89663a

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -446,6 +446,7 @@ config ARCH_MXC 
	select CLKSRC_MMIO

	select GENERIC_IRQ_CHIP

	select MULTI_IRQ_HANDLER

	select SPARSE_IRQ

	help

	  Support for Freescale MXC/iMX-based family of processors

arch/arm/plat-mxc/include/mach/irqs.h

+0 −44
Original line number Diff line number Diff line
@@ -11,50 +11,6 @@ 
#ifndef __ASM_ARCH_MXC_IRQS_H__

#define __ASM_ARCH_MXC_IRQS_H__



#include <asm-generic/gpio.h>



/*

 * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC

 * have 128 IRQs, and those with AVIC have 64.

 *

 * To support single image, the biggest number should be defined on

 * top of the list.

 */

#if defined CONFIG_ARM_GIC

#define MXC_INTERNAL_IRQS	160

#elif defined CONFIG_MXC_TZIC

#define MXC_INTERNAL_IRQS	128

#else

#define MXC_INTERNAL_IRQS	64

#endif



#define MXC_GPIO_IRQ_START	MXC_INTERNAL_IRQS



/*

 * The next 16 interrupts are for board specific purposes.  Since

 * the kernel can only run on one machine at a time, we can re-use

 * these.  If you need more, increase MXC_BOARD_IRQS, but keep it

 * within sensible limits.

 */

#define MXC_BOARD_IRQ_START	(MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)



#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1

#define MXC_BOARD_IRQS  80

#else

#define MXC_BOARD_IRQS	16

#endif



#define MXC_IPU_IRQ_START	(MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)



#ifdef CONFIG_MX3_IPU_IRQS

#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS

#else

#define MX3_IPU_IRQS 0

#endif

/* REVISIT: Add IPU irqs on IMX51 */



#define NR_IRQS			(MXC_IPU_IRQ_START + MX3_IPU_IRQS)



extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);



/* all normal IRQs can be FIQs */

arch/arm/plat-mxc/include/mach/mx1.h

+56 −55
Original line number Diff line number Diff line
@@ -78,61 +78,62 @@ 
#define MX1_IO_ADDRESS(x)		IOMEM(MX1_IO_P2V(x))



/* fixed interrput numbers */

#define MX1_INT_SOFTINT		0

#define MX1_INT_CSI		6

#define MX1_DSPA_MAC_INT	7

#define MX1_DSPA_INT		8

#define MX1_COMP_INT		9

#define MX1_MSHC_XINT		10

#define MX1_GPIO_INT_PORTA	11

#define MX1_GPIO_INT_PORTB	12

#define MX1_GPIO_INT_PORTC	13

#define MX1_INT_LCDC		14

#define MX1_SIM_INT		15

#define MX1_SIM_DATA_INT	16

#define MX1_RTC_INT		17

#define MX1_RTC_SAMINT		18

#define MX1_INT_UART2PFERR	19

#define MX1_INT_UART2RTS	20

#define MX1_INT_UART2DTR	21

#define MX1_INT_UART2UARTC	22

#define MX1_INT_UART2TX		23

#define MX1_INT_UART2RX		24

#define MX1_INT_UART1PFERR	25

#define MX1_INT_UART1RTS	26

#define MX1_INT_UART1DTR	27

#define MX1_INT_UART1UARTC	28

#define MX1_INT_UART1TX		29

#define MX1_INT_UART1RX		30

#define MX1_VOICE_DAC_INT	31

#define MX1_VOICE_ADC_INT	32

#define MX1_PEN_DATA_INT	33

#define MX1_PWM_INT		34

#define MX1_SDHC_INT		35

#define MX1_INT_I2C		39

#define MX1_INT_CSPI2		40

#define MX1_INT_CSPI1		41

#define MX1_SSI_TX_INT		42

#define MX1_SSI_TX_ERR_INT	43

#define MX1_SSI_RX_INT		44

#define MX1_SSI_RX_ERR_INT	45

#define MX1_TOUCH_INT		46

#define MX1_INT_USBD0		47

#define MX1_INT_USBD1		48

#define MX1_INT_USBD2		49

#define MX1_INT_USBD3		50

#define MX1_INT_USBD4		51

#define MX1_INT_USBD5		52

#define MX1_INT_USBD6		53

#define MX1_BTSYS_INT		55

#define MX1_BTTIM_INT		56

#define MX1_BTWUI_INT		57

#define MX1_TIM2_INT		58

#define MX1_TIM1_INT		59

#define MX1_DMA_ERR		60

#define MX1_DMA_INT		61

#define MX1_GPIO_INT_PORTD	62

#define MX1_WDT_INT		63

#include <asm/irq.h>

#define MX1_INT_SOFTINT		(NR_IRQS_LEGACY + 0)

#define MX1_INT_CSI		(NR_IRQS_LEGACY + 6)

#define MX1_DSPA_MAC_INT	(NR_IRQS_LEGACY + 7)

#define MX1_DSPA_INT		(NR_IRQS_LEGACY + 8)

#define MX1_COMP_INT		(NR_IRQS_LEGACY + 9)

#define MX1_MSHC_XINT		(NR_IRQS_LEGACY + 10)

#define MX1_GPIO_INT_PORTA	(NR_IRQS_LEGACY + 11)

#define MX1_GPIO_INT_PORTB	(NR_IRQS_LEGACY + 12)

#define MX1_GPIO_INT_PORTC	(NR_IRQS_LEGACY + 13)

#define MX1_INT_LCDC		(NR_IRQS_LEGACY + 14)

#define MX1_SIM_INT		(NR_IRQS_LEGACY + 15)

#define MX1_SIM_DATA_INT	(NR_IRQS_LEGACY + 16)

#define MX1_RTC_INT		(NR_IRQS_LEGACY + 17)

#define MX1_RTC_SAMINT		(NR_IRQS_LEGACY + 18)

#define MX1_INT_UART2PFERR	(NR_IRQS_LEGACY + 19)

#define MX1_INT_UART2RTS	(NR_IRQS_LEGACY + 20)

#define MX1_INT_UART2DTR	(NR_IRQS_LEGACY + 21)

#define MX1_INT_UART2UARTC	(NR_IRQS_LEGACY + 22)

#define MX1_INT_UART2TX		(NR_IRQS_LEGACY + 23)

#define MX1_INT_UART2RX		(NR_IRQS_LEGACY + 24)

#define MX1_INT_UART1PFERR	(NR_IRQS_LEGACY + 25)

#define MX1_INT_UART1RTS	(NR_IRQS_LEGACY + 26)

#define MX1_INT_UART1DTR	(NR_IRQS_LEGACY + 27)

#define MX1_INT_UART1UARTC	(NR_IRQS_LEGACY + 28)

#define MX1_INT_UART1TX		(NR_IRQS_LEGACY + 29)

#define MX1_INT_UART1RX		(NR_IRQS_LEGACY + 30)

#define MX1_VOICE_DAC_INT	(NR_IRQS_LEGACY + 31)

#define MX1_VOICE_ADC_INT	(NR_IRQS_LEGACY + 32)

#define MX1_PEN_DATA_INT	(NR_IRQS_LEGACY + 33)

#define MX1_PWM_INT		(NR_IRQS_LEGACY + 34)

#define MX1_SDHC_INT		(NR_IRQS_LEGACY + 35)

#define MX1_INT_I2C		(NR_IRQS_LEGACY + 39)

#define MX1_INT_CSPI2		(NR_IRQS_LEGACY + 40)

#define MX1_INT_CSPI1		(NR_IRQS_LEGACY + 41)

#define MX1_SSI_TX_INT		(NR_IRQS_LEGACY + 42)

#define MX1_SSI_TX_ERR_INT	(NR_IRQS_LEGACY + 43)

#define MX1_SSI_RX_INT		(NR_IRQS_LEGACY + 44)

#define MX1_SSI_RX_ERR_INT	(NR_IRQS_LEGACY + 45)

#define MX1_TOUCH_INT		(NR_IRQS_LEGACY + 46)

#define MX1_INT_USBD0		(NR_IRQS_LEGACY + 47)

#define MX1_INT_USBD1		(NR_IRQS_LEGACY + 48)

#define MX1_INT_USBD2		(NR_IRQS_LEGACY + 49)

#define MX1_INT_USBD3		(NR_IRQS_LEGACY + 50)

#define MX1_INT_USBD4		(NR_IRQS_LEGACY + 51)

#define MX1_INT_USBD5		(NR_IRQS_LEGACY + 52)

#define MX1_INT_USBD6		(NR_IRQS_LEGACY + 53)

#define MX1_BTSYS_INT		(NR_IRQS_LEGACY + 55)

#define MX1_BTTIM_INT		(NR_IRQS_LEGACY + 56)

#define MX1_BTWUI_INT		(NR_IRQS_LEGACY + 57)

#define MX1_TIM2_INT		(NR_IRQS_LEGACY + 58)

#define MX1_TIM1_INT		(NR_IRQS_LEGACY + 59)

#define MX1_DMA_ERR		(NR_IRQS_LEGACY + 60)

#define MX1_DMA_INT		(NR_IRQS_LEGACY + 61)

#define MX1_GPIO_INT_PORTD	(NR_IRQS_LEGACY + 62)

#define MX1_WDT_INT		(NR_IRQS_LEGACY + 63)



/* DMA */

#define MX1_DMA_REQ_UART3_T		2

arch/arm/plat-mxc/include/mach/mx21.h

+54 −53
Original line number Diff line number Diff line
@@ -99,59 +99,60 @@ 
#define MX21_IO_ADDRESS(x)		IOMEM(MX21_IO_P2V(x))



/* fixed interrupt numbers */

#define MX21_INT_CSPI3		6

#define MX21_INT_GPIO		8

#define MX21_INT_FIRI		9

#define MX21_INT_SDHC2		10

#define MX21_INT_SDHC1		11

#define MX21_INT_I2C		12

#define MX21_INT_SSI2		13

#define MX21_INT_SSI1		14

#define MX21_INT_CSPI2		15

#define MX21_INT_CSPI1		16

#define MX21_INT_UART4		17

#define MX21_INT_UART3		18

#define MX21_INT_UART2		19

#define MX21_INT_UART1		20

#define MX21_INT_KPP		21

#define MX21_INT_RTC		22

#define MX21_INT_PWM		23

#define MX21_INT_GPT3		24

#define MX21_INT_GPT2		25

#define MX21_INT_GPT1		26

#define MX21_INT_WDOG		27

#define MX21_INT_PCMCIA		28

#define MX21_INT_NFC		29

#define MX21_INT_BMI		30

#define MX21_INT_CSI		31

#define MX21_INT_DMACH0		32

#define MX21_INT_DMACH1		33

#define MX21_INT_DMACH2		34

#define MX21_INT_DMACH3		35

#define MX21_INT_DMACH4		36

#define MX21_INT_DMACH5		37

#define MX21_INT_DMACH6		38

#define MX21_INT_DMACH7		39

#define MX21_INT_DMACH8		40

#define MX21_INT_DMACH9		41

#define MX21_INT_DMACH10	42

#define MX21_INT_DMACH11	43

#define MX21_INT_DMACH12	44

#define MX21_INT_DMACH13	45

#define MX21_INT_DMACH14	46

#define MX21_INT_DMACH15	47

#define MX21_INT_EMMAENC	49

#define MX21_INT_EMMADEC	50

#define MX21_INT_EMMAPRP	51

#define MX21_INT_EMMAPP		52

#define MX21_INT_USBWKUP	53

#define MX21_INT_USBDMA		54

#define MX21_INT_USBHOST	55

#define MX21_INT_USBFUNC	56

#define MX21_INT_USBMNP		57

#define MX21_INT_USBCTRL	58

#define MX21_INT_SLCDC		60

#define MX21_INT_LCDC		61

#include <asm/irq.h>

#define MX21_INT_CSPI3		(NR_IRQS_LEGACY + 6)

#define MX21_INT_GPIO		(NR_IRQS_LEGACY + 8)

#define MX21_INT_FIRI		(NR_IRQS_LEGACY + 9)

#define MX21_INT_SDHC2		(NR_IRQS_LEGACY + 10)

#define MX21_INT_SDHC1		(NR_IRQS_LEGACY + 11)

#define MX21_INT_I2C		(NR_IRQS_LEGACY + 12)

#define MX21_INT_SSI2		(NR_IRQS_LEGACY + 13)

#define MX21_INT_SSI1		(NR_IRQS_LEGACY + 14)

#define MX21_INT_CSPI2		(NR_IRQS_LEGACY + 15)

#define MX21_INT_CSPI1		(NR_IRQS_LEGACY + 16)

#define MX21_INT_UART4		(NR_IRQS_LEGACY + 17)

#define MX21_INT_UART3		(NR_IRQS_LEGACY + 18)

#define MX21_INT_UART2		(NR_IRQS_LEGACY + 19)

#define MX21_INT_UART1		(NR_IRQS_LEGACY + 20)

#define MX21_INT_KPP		(NR_IRQS_LEGACY + 21)

#define MX21_INT_RTC		(NR_IRQS_LEGACY + 22)

#define MX21_INT_PWM		(NR_IRQS_LEGACY + 23)

#define MX21_INT_GPT3		(NR_IRQS_LEGACY + 24)

#define MX21_INT_GPT2		(NR_IRQS_LEGACY + 25)

#define MX21_INT_GPT1		(NR_IRQS_LEGACY + 26)

#define MX21_INT_WDOG		(NR_IRQS_LEGACY + 27)

#define MX21_INT_PCMCIA		(NR_IRQS_LEGACY + 28)

#define MX21_INT_NFC		(NR_IRQS_LEGACY + 29)

#define MX21_INT_BMI		(NR_IRQS_LEGACY + 30)

#define MX21_INT_CSI		(NR_IRQS_LEGACY + 31)

#define MX21_INT_DMACH0		(NR_IRQS_LEGACY + 32)

#define MX21_INT_DMACH1		(NR_IRQS_LEGACY + 33)

#define MX21_INT_DMACH2		(NR_IRQS_LEGACY + 34)

#define MX21_INT_DMACH3		(NR_IRQS_LEGACY + 35)

#define MX21_INT_DMACH4		(NR_IRQS_LEGACY + 36)

#define MX21_INT_DMACH5		(NR_IRQS_LEGACY + 37)

#define MX21_INT_DMACH6		(NR_IRQS_LEGACY + 38)

#define MX21_INT_DMACH7		(NR_IRQS_LEGACY + 39)

#define MX21_INT_DMACH8		(NR_IRQS_LEGACY + 40)

#define MX21_INT_DMACH9		(NR_IRQS_LEGACY + 41)

#define MX21_INT_DMACH10	(NR_IRQS_LEGACY + 42)

#define MX21_INT_DMACH11	(NR_IRQS_LEGACY + 43)

#define MX21_INT_DMACH12	(NR_IRQS_LEGACY + 44)

#define MX21_INT_DMACH13	(NR_IRQS_LEGACY + 45)

#define MX21_INT_DMACH14	(NR_IRQS_LEGACY + 46)

#define MX21_INT_DMACH15	(NR_IRQS_LEGACY + 47)

#define MX21_INT_EMMAENC	(NR_IRQS_LEGACY + 49)

#define MX21_INT_EMMADEC	(NR_IRQS_LEGACY + 50)

#define MX21_INT_EMMAPRP	(NR_IRQS_LEGACY + 51)

#define MX21_INT_EMMAPP		(NR_IRQS_LEGACY + 52)

#define MX21_INT_USBWKUP	(NR_IRQS_LEGACY + 53)

#define MX21_INT_USBDMA		(NR_IRQS_LEGACY + 54)

#define MX21_INT_USBHOST	(NR_IRQS_LEGACY + 55)

#define MX21_INT_USBFUNC	(NR_IRQS_LEGACY + 56)

#define MX21_INT_USBMNP		(NR_IRQS_LEGACY + 57)

#define MX21_INT_USBCTRL	(NR_IRQS_LEGACY + 58)

#define MX21_INT_SLCDC		(NR_IRQS_LEGACY + 60)

#define MX21_INT_LCDC		(NR_IRQS_LEGACY + 61)



/* fixed DMA request numbers */

#define MX21_DMA_REQ_CSPI3_RX	1

arch/arm/plat-mxc/include/mach/mx25.h

+38 −34
Original line number Diff line number Diff line
@@ -61,40 +61,44 @@ 
#define MX25_IO_P2V(x)			IMX_IO_P2V(x)

#define MX25_IO_ADDRESS(x)		IOMEM(MX25_IO_P2V(x))



#define MX25_INT_CSPI3		0

#define MX25_INT_I2C1		3

#define MX25_INT_I2C2		4

#define MX25_INT_UART4		5

#define MX25_INT_ESDHC2		8

#define MX25_INT_ESDHC1		9

#define MX25_INT_I2C3		10

#define MX25_INT_SSI2		11

#define MX25_INT_SSI1		12

#define MX25_INT_CSPI2		13

#define MX25_INT_CSPI1		14

#define MX25_INT_GPIO3		16

#define MX25_INT_CSI		17

#define MX25_INT_UART3		18

#define MX25_INT_GPIO4		23

#define MX25_INT_KPP		24

#define MX25_INT_DRYICE		25

#define MX25_INT_PWM1		26

#define MX25_INT_UART2		32

#define MX25_INT_NFC		33

#define MX25_INT_SDMA		34

#define MX25_INT_USB_HS		35

#define MX25_INT_PWM2		36

#define MX25_INT_USB_OTG	37

#define MX25_INT_LCDC		39

#define MX25_INT_UART5		40

#define MX25_INT_PWM3		41

#define MX25_INT_PWM4		42

#define MX25_INT_CAN1		43

#define MX25_INT_CAN2		44

#define MX25_INT_UART1		45

#define MX25_INT_GPIO2		51

#define MX25_INT_GPIO1		52

#define MX25_INT_FEC		57

/*

 * Interrupt numbers

 */

#include <asm/irq.h>

#define MX25_INT_CSPI3		(NR_IRQS_LEGACY + 0)

#define MX25_INT_I2C1		(NR_IRQS_LEGACY + 3)

#define MX25_INT_I2C2		(NR_IRQS_LEGACY + 4)

#define MX25_INT_UART4		(NR_IRQS_LEGACY + 5)

#define MX25_INT_ESDHC2		(NR_IRQS_LEGACY + 8)

#define MX25_INT_ESDHC1		(NR_IRQS_LEGACY + 9)

#define MX25_INT_I2C3		(NR_IRQS_LEGACY + 10)

#define MX25_INT_SSI2		(NR_IRQS_LEGACY + 11)

#define MX25_INT_SSI1		(NR_IRQS_LEGACY + 12)

#define MX25_INT_CSPI2		(NR_IRQS_LEGACY + 13)

#define MX25_INT_CSPI1		(NR_IRQS_LEGACY + 14)

#define MX25_INT_GPIO3		(NR_IRQS_LEGACY + 16)

#define MX25_INT_CSI		(NR_IRQS_LEGACY + 17)

#define MX25_INT_UART3		(NR_IRQS_LEGACY + 18)

#define MX25_INT_GPIO4		(NR_IRQS_LEGACY + 23)

#define MX25_INT_KPP		(NR_IRQS_LEGACY + 24)

#define MX25_INT_DRYICE		(NR_IRQS_LEGACY + 25)

#define MX25_INT_PWM1		(NR_IRQS_LEGACY + 26)

#define MX25_INT_UART2		(NR_IRQS_LEGACY + 32)

#define MX25_INT_NFC		(NR_IRQS_LEGACY + 33)

#define MX25_INT_SDMA		(NR_IRQS_LEGACY + 34)

#define MX25_INT_USB_HS		(NR_IRQS_LEGACY + 35)

#define MX25_INT_PWM2		(NR_IRQS_LEGACY + 36)

#define MX25_INT_USB_OTG	(NR_IRQS_LEGACY + 37)

#define MX25_INT_LCDC		(NR_IRQS_LEGACY + 39)

#define MX25_INT_UART5		(NR_IRQS_LEGACY + 40)

#define MX25_INT_PWM3		(NR_IRQS_LEGACY + 41)

#define MX25_INT_PWM4		(NR_IRQS_LEGACY + 42)

#define MX25_INT_CAN1		(NR_IRQS_LEGACY + 43)

#define MX25_INT_CAN2		(NR_IRQS_LEGACY + 44)

#define MX25_INT_UART1		(NR_IRQS_LEGACY + 45)

#define MX25_INT_GPIO2		(NR_IRQS_LEGACY + 51)

#define MX25_INT_GPIO1		(NR_IRQS_LEGACY + 52)

#define MX25_INT_FEC		(NR_IRQS_LEGACY + 57)



#define MX25_DMA_REQ_SSI2_RX1	22

#define MX25_DMA_REQ_SSI2_TX1	23

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