Commit 88404312 authored Jun 23, 2017 by Xiaolei Li Committed by Boris Brezillon Jun 25, 2017

mtd: nand: mtk: disable ecc irq when writing page with hwecc



Currently, ecc encode irq is enabled when writing page with hwecc, but
we actually do not wait for this irq done. Because NFI and ECC work in
parallel, nfi irq and ecc irq almost come together.

Now, there are two steps to check whether page data are totally written.
First, wait for nfi irq INTR_AHB_DONE. This is to ensure all data
in RAM are received by NFI.
Second, polling the register NFI_ADDRCNTR till all data include ecc
parity data runtime generated by ECC are sent to NAND device.

So, it is redunant to enable ecc irq without waiting for it.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

parent 188986c7

drivers/mtd/nand/mtk_ecc.c

+12 −10

Original line number	Diff line number	Diff line
		@@ -276,6 +276,7 @@ int mtk_ecc_enable(struct mtk_ecc ecc, struct mtk_ecc_config config)
		if (ret)
		return ret;

		if (config->mode != ECC_NFI_MODE \|\| op != ECC_ENCODE) {
		init_completion(&ecc->done);
		reg_val = ECC_IRQ_EN;
		/*
		@@ -283,9 +284,10 @@ int mtk_ecc_enable(struct mtk_ecc ecc, struct mtk_ecc_config config)
		* means this chip can only generate one ecc irq during page
		* read / write. If is 0, generate one ecc irq each ecc step.
		*/
		if ((ecc->caps->pg_irq_sel) && (config->mode == ECC_NFI_MODE))
		if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
		reg_val \|= ECC_PG_IRQ_SEL;
		writew(reg_val, ecc->regs + ECC_IRQ_REG(op));
		}

		writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));

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