Merge tag 'socfpga_update_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next into next/dt

Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]

The EDAC accesses a range of registers in the SDRAM controller.

Required properties:

- compatible : should contain "altr,sdram-edac";

- altr,sdr-syscon : phandle of the sdr module

- interrupts : Should contain the SDRAM ECC IRQ in the

	appropriate format for the IRQ controller.

Example:

	sdramedac {

		compatible = "altr,sdram-edac";

		altr,sdr-syscon = <&sdr>;

		interrupts = <0 39 4>;

	};

1) Interrupt client nodes

-------------------------

Nodes that describe devices which generate interrupts must contain an either an

"interrupts" property or an "interrupts-extended" property. These properties

contain a list of interrupt specifiers, one per output interrupt. The format of

the interrupt specifier is determined by the interrupt controller to which the

interrupts are routed; see section 2 below for details.

Nodes that describe devices which generate interrupts must contain an

"interrupts" property, an "interrupts-extended" property, or both. If both are

present, the latter should take precedence; the former may be provided simply

for compatibility with software that does not recognize the latter. These

properties contain a list of interrupt specifiers, one per output interrupt. The

format of the interrupt specifier is determined by the interrupt controller to

which the interrupts are routed; see section 2 below for details.

  Example:

	interrupt-parent = <&intc1>;

Required properties:

- compatible: should contain "snps,dw-pcie" to identify the core.

- reg: Should contain the configuration address space.

- reg-names: Must be "config" for the PCIe configuration space.

    (The old way of getting the configuration address space from "ranges"

    is deprecated and should be avoided.)

- #address-cells: set to <3>

- #size-cells: set to <2>

- device_type: set to "pci"

TI PCI Controllers

PCIe Designware Controller

 - compatible: Should be "ti,dra7-pcie""

 - reg : Two register ranges as listed in the reg-names property

 - reg-names : The first entry must be "ti-conf" for the TI specific registers

	       The second entry must be "rc-dbics" for the designware pcie

	       registers

	       The third entry must be "config" for the PCIe configuration space

 - phys : list of PHY specifiers (used by generic PHY framework)

 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the

	       number of PHYs as specified in *phys* property.

 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",

	       where <X> is the instance number of the pcie from the HW spec.

 - interrupts : Two interrupt entries must be specified. The first one is for

		main interrupt line and the second for MSI interrupt line.

 - #address-cells,

   #size-cells,

   #interrupt-cells,

   device_type,

   ranges,

   num-lanes,

   interrupt-map-mask,

   interrupt-map : as specified in ../designware-pcie.txt

Example:

axi {

	compatible = "simple-bus";

	#size-cells = <1>;

	#address-cells = <1>;

	ranges = <0x51000000 0x51000000 0x3000

		  0x0	     0x20000000 0x10000000>;

	pcie@51000000 {

		compatible = "ti,dra7-pcie";

		reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;

		reg-names = "rc_dbics", "ti_conf", "config";

		interrupts = <0 232 0x4>, <0 233 0x4>;

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x81000000 0 0          0x03000 0 0x00010000

			  0x82000000 0 0x20013000 0x13000 0 0xffed000>;

		#interrupt-cells = <1>;

		num-lanes = <1>;

		ti,hwmods = "pcie1";

		phys = <&pcie1_phy>;

		phy-names = "pcie-phy0";

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc 1>,

				<0 0 0 2 &pcie_intc 2>,

				<0 0 0 3 &pcie_intc 3>,

				<0 0 0 4 &pcie_intc 4>;

		pcie_intc: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};

};

profiles.  If you believe that individual invalidations being

called too often, you can lower the tunable:

	/sys/debug/kernel/x86/tlb_single_page_flush_ceiling

	/sys/kernel/debug/x86/tlb_single_page_flush_ceiling

This will cause us to do the global flush for more cases.

Lowering it to 0 will disable the use of the individual flushes.