Commit 87e5fe5b authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Will Deacon
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iommu/arm-smmu-v3: Write level-1 descriptors atomically 



Use WRITE_ONCE() to make sure that the SMMU doesn't read incomplete
stream table descriptors. Refer to the comment about 64-bit accesses,
and add the comment to the equivalent context descriptor code.

Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 058c59a0

drivers/iommu/arm-smmu-v3.c

+3 −1
Original line number Diff line number Diff line
@@ -1531,6 +1531,7 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, 
	u64 val = (l1_desc->l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) |

		  CTXDESC_L1_DESC_V;



	/* See comment in arm_smmu_write_ctx_desc() */

	WRITE_ONCE(*dst, cpu_to_le64(val));

}
@@ -1726,7 +1727,8 @@ arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc) 
	val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span);

	val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK;



	*dst = cpu_to_le64(val);

	/* See comment in arm_smmu_write_ctx_desc() */

	WRITE_ONCE(*dst, cpu_to_le64(val));

}



static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)

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