dt-bindings: timer: add Tegra210 timer

NVIDIA Tegra210 timer

The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit

timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived

from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock

(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,

or watchdog interrupts.

Required properties:

- compatible : "nvidia,tegra210-timer".

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 14 interrupts; one per each timer channels 0 through

  13.

- clocks : Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.

timer@60005000 {

	compatible = "nvidia,tegra210-timer";

	reg = <0x0 0x60005000 0x0 0x400>;

	interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_TIMER>;

	clock-names = "timer";

};