drm/amd/display: Reset steer fifo before unblanking the stream (87de6cb2) · Commits · 戴 / test

[why] During mode transition steer fifo could overflow. Quite often it recovers by itself, but sometimes it doesn't. [how] Add steer fifo reset before unblanking the stream. Also add a short delay when resetting dig resync fifo to make sure register writes don't end up back-to-back, in which case the HW might miss the reset request. Signed-off-by:

Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:

Tony Cheng <Tony.Cheng@amd.com> Acked-by:

Leo Li <sunpeng.li@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -492,15 +492,23 @@ void enc2_stream_encoder_dp_unblank(
		DP_VID_N_MUL, n_multiply);
		}

		/* set DIG_START to 0x1 to reset FIFO */
		/* make sure stream is disabled before resetting steer fifo */
		REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
		REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);

		/* set DIG_START to 0x1 to reset FIFO */
		REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
		udelay(1);

		/* write 0 to take the FIFO out of reset */

		REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);

		/* switch DP encoder to CRTC data */
		/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
		* that it overflows during mode transition, and sometimes doesn't recover.
		*/
		REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
		udelay(10);

		REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

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