Commit 87d7bcee authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 

Pull crypto update from Herbert Xu:
 - add multibuffer infrastructure (single_task_running scheduler helper,
   OKed by Peter on lkml.
 - add SHA1 multibuffer implementation for AVX2.
 - reenable "by8" AVX CTR optimisation after fixing counter overflow.
 - add APM X-Gene SoC RNG support.
 - SHA256/SHA512 now handles unaligned input correctly.
 - set lz4 decompressed length correctly.
 - fix algif socket buffer allocation failure for 64K page machines.
 - misc fixes

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (47 commits)
  crypto: sha - Handle unaligned input data in generic sha256 and sha512.
  Revert "crypto: aesni - disable "by8" AVX CTR optimization"
  crypto: aesni - remove unused defines in "by8" variant
  crypto: aesni - fix counter overflow handling in "by8" variant
  hwrng: printk replacement
  crypto: qat - Removed unneeded partial state
  crypto: qat - Fix typo in name of tasklet_struct
  crypto: caam - Dynamic allocation of addresses for various memory blocks in CAAM.
  crypto: mcryptd - Fix typos in CRYPTO_MCRYPTD description
  crypto: algif - avoid excessive use of socket buffer in skcipher
  arm64: dts: add random number generator dts node to APM X-Gene platform.
  Documentation: rng: Add X-Gene SoC RNG driver documentation
  hwrng: xgene - add support for APM X-Gene SoC RNG support
  crypto: mv_cesa - Add missing #define
  crypto: testmgr - add test for lz4 and lz4hc
  crypto: lz4,lz4hc - fix decompression
  crypto: qat - Use pci_enable_msix_exact() instead of pci_enable_msix()
  crypto: drbg - fix maximum value checks on 32 bit systems
  crypto: drbg - fix sparse warning for cpu_to_be[32|64]
  crypto: sha-mb - sha1_mb_alg_state can be static
  ...
parents 0223f9aa be34c4ef

Documentation/devicetree/bindings/rng/apm,rng.txt

0 → 100644
+17 −0
Original line number Diff line number Diff line 
APM X-Gene SoC random number generator.



Required properties:



- compatible  : should be "apm,xgene-rng"

- reg         : specifies base physical address and size of the registers map

- clocks      : phandle to clock-controller plus clock-specifier pair

- interrupts  : specify the fault interrupt for the RNG device



Example:



	rng: rng@10520000 {

		compatible = "apm,xgene-rng";

		reg = <0x0 0x10520000 0x0 0x100>;

		interrupts =   <0x0 0x41 0x4>;

		clocks = <&rngpkaclk 0>;

	};

arch/arm64/boot/dts/apm-storm.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -269,6 +269,19 @@ 
				enable-mask = <0x2>;

				clock-output-names = "rtcclk";

			};



			rngpkaclk: rngpkaclk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg";

				csr-offset = <0xc>;

				csr-mask = <0x10>;

				enable-offset = <0x10>;

				enable-mask = <0x10>;

				clock-output-names = "rngpkaclk";

			};

		};



		serial0: serial@1c020000 {
@@ -421,5 +434,13 @@ 


			};

		};



		rng: rng@10520000 {

			compatible = "apm,xgene-rng";

			reg = <0x0 0x10520000 0x0 0x100>;

			interrupts = <0x0 0x41 0x4>;

			clocks = <&rngpkaclk 0>;

		};



	};

};

arch/x86/crypto/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o 


obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o

obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o

obj-$(CONFIG_CRYPTO_SHA1_MB) += sha-mb/

obj-$(CONFIG_CRYPTO_CRC32_PCLMUL) += crc32-pclmul.o

obj-$(CONFIG_CRYPTO_SHA256_SSSE3) += sha256-ssse3.o

obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o

arch/x86/crypto/aes_ctrby8_avx-x86_64.S

+15 −5
Original line number Diff line number Diff line
@@ -79,9 +79,6 @@ 
#define xcounter	%xmm8

#define xbyteswap	%xmm9

#define xkey0		%xmm10

#define xkey3		%xmm11

#define xkey6		%xmm12

#define xkey9		%xmm13

#define xkey4		%xmm11

#define xkey8		%xmm12

#define xkey12		%xmm13
@@ -108,6 +105,10 @@ 


byteswap_const:

	.octa 0x000102030405060708090A0B0C0D0E0F

ddq_low_msk:

	.octa 0x0000000000000000FFFFFFFFFFFFFFFF

ddq_high_add_1:

	.octa 0x00000000000000010000000000000000

ddq_add_1:

	.octa 0x00000000000000000000000000000001

ddq_add_2:
@@ -169,7 +170,12 @@ ddq_add_8: 
	.rept (by - 1)

		club DDQ_DATA, i

		club XDATA, i

		vpaddd	var_ddq_add(%rip), xcounter, var_xdata

		vpaddq	var_ddq_add(%rip), xcounter, var_xdata

		vptest	ddq_low_msk(%rip), var_xdata

		jnz 1f

		vpaddq	ddq_high_add_1(%rip), var_xdata, var_xdata

		vpaddq	ddq_high_add_1(%rip), xcounter, xcounter

		1:

		vpshufb	xbyteswap, var_xdata, var_xdata

		.set i, (i +1)

	.endr
@@ -178,7 +184,11 @@ ddq_add_8: 


	vpxor	xkey0, xdata0, xdata0

	club DDQ_DATA, by

	vpaddd	var_ddq_add(%rip), xcounter, xcounter

	vpaddq	var_ddq_add(%rip), xcounter, xcounter

	vptest	ddq_low_msk(%rip), xcounter

	jnz	1f

	vpaddq	ddq_high_add_1(%rip), xcounter, xcounter

	1:



	.set i, 1

	.rept (by - 1)

arch/x86/crypto/aesni-intel_glue.c

+2 −2
Original line number Diff line number Diff line
@@ -481,7 +481,7 @@ static void ctr_crypt_final(struct crypto_aes_ctx *ctx, 
	crypto_inc(ctrblk, AES_BLOCK_SIZE);

}



#if 0	/* temporary disabled due to failing crypto tests */

#ifdef CONFIG_AS_AVX

static void aesni_ctr_enc_avx_tfm(struct crypto_aes_ctx *ctx, u8 *out,

			      const u8 *in, unsigned int len, u8 *iv)

{
@@ -1522,7 +1522,7 @@ static int __init aesni_init(void) 
		aesni_gcm_dec_tfm = aesni_gcm_dec;

	}

	aesni_ctr_enc_tfm = aesni_ctr_enc;

#if 0	/* temporary disabled due to failing crypto tests */

#ifdef CONFIG_AS_AVX

	if (cpu_has_avx) {

		/* optimize performance of ctr mode encryption transform */

		aesni_ctr_enc_tfm = aesni_ctr_enc_avx_tfm;

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