drm/i915: Fix ICL output CSC programming (879a4e70) · Commits · 戴 / test

When I refactored the code into its own function I accidentally misplaced the <<16 shifts for some of the registers causing us to lose the blue channel entirely. We should really find a way to test this... Cc: Uma Shankar <uma.shankar@intel.com> Fixes: ("drm/i915: Clean up ilk/icl pipe/output CSC programming") Signed-off-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190425192419.24931-1-ville.syrjala@linux.intel.com Reviewed-by:

Swati Sharma <swati2.sharma@intel.com> (cherry picked from commit ) Signed-off-by:

Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

drivers/gpu/drm/i915/intel_color.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -173,13 +173,13 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);

		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 \| coeff[1]);
		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16);

		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 \| coeff[4]);
		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16);

		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 \| coeff[7]);
		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16);

		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);

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