Commit 8784692d authored by Abhishek Pandit-Subedi's avatar Abhishek Pandit-Subedi Committed by Heiko Stuebner
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ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron 



This enables the Broadcom uart bluetooth driver on uart0 and gives it
ownership of its gpios. In order to use this, you must enable the
following kconfig options:
- CONFIG_BT_HCIUART_BCM
- CONFIG_SERIAL_DEV

This is applicable to rk3288-veyron series boards that use the bcm43540
wifi+bt chips.

As part of this change, also refactor the pinctrl across the various
boards. All the boards using broadcom bluetooth shouldn't touch the
bt_dev_wake pin.

Signed-off-by: default avatarAbhishek Pandit-Subedi <abhishekpandit@chromium.org>
Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20191127223909.253873-2-abhishekpandit@chromium.org


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent e42617b8

arch/arm/boot/dts/rk3288-veyron-brain.dts

+9 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


/dts-v1/;

#include "rk3288-veyron.dtsi"

#include "rk3288-veyron-broadcom-bluetooth.dtsi"



/ {

	model = "Google Brain";
@@ -40,6 +41,14 @@ 
};



&pinctrl {

	pinctrl-names = "default";

	pinctrl-0 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff

	>;



	hdmi {

		vcc50_hdmi_en: vcc50-hdmi-en {

			rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;

arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi

0 → 100644
+22 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth

 * chip.

 *

 * Copyright 2019 Google, Inc

 */



&uart0 {

	bluetooth {

		pinctrl-names = "default";

		pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,

			    <&bt_dev_wake>;



		compatible = "brcm,bcm43540-bt";

		host-wakeup-gpios	= <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;

		shutdown-gpios		= <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;

		device-wakeup-gpios	= <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;

		max-speed		= <3000000>;

		brcm,bt-pcm-int-params	= [01 02 00 01 01];

	};

};

arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi

+0 −21
Original line number Diff line number Diff line
@@ -136,27 +136,6 @@ 
};



&pinctrl {

	pinctrl-0 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Wake only */

		&suspend_l_wake

		&bt_dev_wake_awake

	>;

	pinctrl-1 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Sleep only */

		&suspend_l_sleep

		&bt_dev_wake_sleep

	>;



	buttons {

		ap_lid_int_l: ap-lid-int-l {

			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;

arch/arm/boot/dts/rk3288-veyron-fievel.dts

+0 −2
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ 
		     "google,veyron-fievel-rev0", "google,veyron-fievel",

		     "google,veyron", "rockchip,rk3288";



	/delete-node/ bt-activity;



	vccsys: vccsys {

		compatible = "regulator-fixed";

		regulator-name = "vccsys";

arch/arm/boot/dts/rk3288-veyron-jaq.dts

+22 −0
Original line number Diff line number Diff line
@@ -273,6 +273,28 @@ 
};



&pinctrl {

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Wake only */

		&suspend_l_wake

		&bt_dev_wake_awake

	>;

	pinctrl-1 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Sleep only */

		&suspend_l_sleep

		&bt_dev_wake_sleep

	>;



	buck-5v {

		drv_5v: drv-5v {

			rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;

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