Commit 8781e5df authored by Dennis Li's avatar Dennis Li Committed by Alex Deucher
Browse files

drm/amdgpu: refine query function of mmhub EDC counter in vg20 



Add codes to print the detail EDC info for the subblock of mmhub

v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header
files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local
static variable and function.

v3: squash in DC fix

Signed-off-by: default avatarDennis Li <dennis.li@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 46f71969

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+180 −52
Original line number Diff line number Diff line
@@ -27,17 +27,13 @@ 
#include "mmhub/mmhub_1_0_offset.h"

#include "mmhub/mmhub_1_0_sh_mask.h"

#include "mmhub/mmhub_1_0_default.h"

#include "mmhub/mmhub_9_4_0_offset.h"

#include "vega10_enum.h"



#include "soc15.h"

#include "soc15_common.h"



#define mmDAGB0_CNTL_MISC2_RV 0x008f

#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0



#define EA_EDC_CNT_MASK 0x3

#define EA_EDC_CNT_SHIFT 0x2



u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)

{

	u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
@@ -562,59 +558,191 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 
		*flags |= AMD_CG_SUPPORT_MC_LS;

}



static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = {

	{ "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),

	},

	{ "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),

	},

	{ "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),

	},

	{ "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),

	},

	{ "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),

	},

	{ "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),

	},

	{ "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),

	},

	{ "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),

	},

	{ "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),

	},

	{ "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),

	},

	{ "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),

	},

	{ "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),

	},

	{ "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),

	},

	{ "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),

	},

	{ "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),

	},

	{ "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),

	},

	{ "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),

	0, 0,

	},

	{ "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),

	SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),

	0, 0,

	}

};



static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = {

   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0},

   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0},

   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0},

   { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0},

};



static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg,

	uint32_t value, uint32_t *sec_count, uint32_t *ded_count)

{

	uint32_t i;

	uint32_t sec_cnt, ded_cnt;



	for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) {

		if(mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)

			continue;



		sec_cnt = (value &

				mmhub_v1_0_ras_fields[i].sec_count_mask) >>

				mmhub_v1_0_ras_fields[i].sec_count_shift;

		if (sec_cnt) {

			DRM_INFO("MMHUB SubBlock %s, SEC %d\n",

				mmhub_v1_0_ras_fields[i].name,

				sec_cnt);

			*sec_count += sec_cnt;

		}



		ded_cnt = (value &

				mmhub_v1_0_ras_fields[i].ded_count_mask) >>

				mmhub_v1_0_ras_fields[i].ded_count_shift;

		if (ded_cnt) {

			DRM_INFO("MMHUB SubBlock %s, DED %d\n",

				mmhub_v1_0_ras_fields[i].name,

				ded_cnt);

			*ded_count += ded_cnt;

		}

	}



	return 0;

}



static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,

					   void *ras_error_status)

{

	int i;

	uint32_t ea0_edc_cnt, ea0_edc_cnt2;

	uint32_t ea1_edc_cnt, ea1_edc_cnt2;

	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;

	uint32_t sec_count = 0, ded_count = 0;

	uint32_t i;

	uint32_t reg_value;



	/* EDC CNT will be cleared automatically after read */

	ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);

	ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);

	ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);

	ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);

	err_data->ue_count = 0;

	err_data->ce_count = 0;



	/* error count of each error type is recorded by 2 bits,

	 * ce and ue count in EDC_CNT

	 */

	for (i = 0; i < 5; i++) {

		err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);

		err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);

		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;

		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);

		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;

	}

	/* successive ue count in EDC_CNT */

	for (i = 0; i < 5; i++) {

		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);

		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;

	}



	/* ce and ue count in EDC_CNT2 */

	for (i = 0; i < 3; i++) {

		err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);

		err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);

		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);

		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

	}

	/* successive ue count in EDC_CNT2 */

	for (i = 0; i < 6; i++) {

		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);

		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);

		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;

	for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) {

		reg_value =

			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));

		if (reg_value)

			mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i],

				reg_value, &sec_count, &ded_count);

	}



	err_data->ce_count += sec_count;

	err_data->ue_count += ded_count;

}



const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

+2 −2
Original line number Diff line number Diff line
@@ -63,8 +63,8 @@ 
#include "soc15_hw_ip.h"

#include "vega10_ip_offset.h"

#include "nbio/nbio_6_1_offset.h"

#include "mmhub/mmhub_9_4_0_offset.h"

#include "mmhub/mmhub_9_4_0_sh_mask.h"

#include "mmhub/mmhub_1_0_offset.h"

#include "mmhub/mmhub_1_0_sh_mask.h"

#include "reg_helper.h"



#include "dce100/dce100_resource.h"

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h

+16 −0
Original line number Diff line number Diff line
@@ -1964,4 +1964,20 @@ 
#define mmATC_L2_PERFCOUNTER_RSLT_CNTL                                                                 0x084a

#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                        0



/* MMEA */

#define mmMMEA0_EDC_CNT_VG20                                                                           0x0206

#define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0

#define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207

#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0

#define mmMMEA1_EDC_CNT_VG20                                                                           0x0346

#define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0

#define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347

#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0



// addressBlock: mmhub_utcl2_vmsharedpfdec

// base address: 0x6a040

#define mmMC_VM_XGMI_LFB_CNTL                                                                          0x0823

#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                                 0

#define mmMC_VM_XGMI_LFB_SIZE                                                                          0x0824

#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                                 0

#endif

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h

+122 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h

deleted100644 → 0
+0 −53
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2018  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _mmhub_9_4_0_OFFSET_HEADER

#define _mmhub_9_4_0_OFFSET_HEADER



/* MMEA */

#define mmMMEA0_SDP_ARB_FINAL_VG20                                                                     0x01ee

#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0

#define mmMMEA0_EDC_CNT_VG20                                                                           0x0206

#define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0

#define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207

#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0

#define mmMMEA0_EDC_MODE_VG20                                                                          0x0210

#define mmMMEA0_EDC_MODE_VG20_BASE_IDX                                                                 0

#define mmMMEA0_ERR_STATUS_VG20                                                                        0x0211

#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX                                                               0

#define mmMMEA1_SDP_ARB_FINAL_VG20                                                                     0x032e

#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0

#define mmMMEA1_EDC_CNT_VG20                                                                           0x0346

#define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0

#define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347

#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0

#define mmMMEA1_EDC_MODE_VG20                                                                          0x0350

#define mmMMEA1_EDC_MODE_VG20_BASE_IDX                                                                 0

#define mmMMEA1_ERR_STATUS_VG20                                                                        0x0351

#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX                                                               0



// addressBlock: mmhub_utcl2_vmsharedpfdec

// base address: 0x6a040

#define mmMC_VM_XGMI_LFB_CNTL                                                                          0x0823

#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                                 0

#define mmMC_VM_XGMI_LFB_SIZE                                                                          0x0824

#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                                 0



#endif

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