Commit 875330f8 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Miquel Raynal
Browse files

mtd: onenand: Use mtd->oops_panic_write as condition 



struct mtd_info has a flag oops_panic_write which is set when the write
operation is issued via the panic_write() callback. That allows controller
drivers to distinguish the panic write from a regular write.

Replace the open coded 'in_interrupt() | oops_in_progress' checks with a
check for that flag. in_interrupt() is an unrealiable indicator anyway as
it covers all sorts of atomic contexts not only hard and soft interrupt
service routines.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Boris Brezillon <boris.brezillon@collabora.com>
Cc: linux-mtd@lists.infradead.org
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20201113141422.2214771-1-bigeasy@linutronix.de
parent 62e5c6c5

drivers/mtd/nand/onenand/onenand_omap2.c

+8 −8
Original line number Diff line number Diff line
@@ -371,12 +371,12 @@ static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area, 


	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;

	/*

	 * If the buffer address is not DMA-able, len is not long enough to make

	 * DMA transfers profitable or panic_write() may be in an interrupt

	 * context fallback to PIO mode.

	 * If the buffer address is not DMA-able, len is not long enough to

	 * make DMA transfers profitable or if invoked from panic_write()

	 * fallback to PIO mode.

	 */

	if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||

	    count < 384 || in_interrupt() || oops_in_progress)

	    count < 384 || mtd->oops_panic_write)

		goto out_copy;



	xtra = count & 3;
@@ -418,12 +418,12 @@ static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area, 


	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;

	/*

	 * If the buffer address is not DMA-able, len is not long enough to make

	 * DMA transfers profitable or panic_write() may be in an interrupt

	 * context fallback to PIO mode.

	 * If the buffer address is not DMA-able, len is not long enough to

	 * make DMA transfers profitable or if invoked from panic_write()

	 * fallback to PIO mode.

	 */

	if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||

	    count < 384 || in_interrupt() || oops_in_progress)

	    count < 384 || mtd->oops_panic_write)

		goto out_copy;



	dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);

drivers/mtd/nand/raw/nand_legacy.c

+5 −4
Original line number Diff line number Diff line
@@ -192,9 +192,10 @@ static void panic_nand_wait_ready(struct nand_chip *chip, unsigned long timeo) 
 */

void nand_wait_ready(struct nand_chip *chip)

{

	struct mtd_info *mtd = nand_to_mtd(chip);

	unsigned long timeo = 400;



	if (in_interrupt() || oops_in_progress)

	if (mtd->oops_panic_write)

		return panic_nand_wait_ready(chip, timeo);



	/* Wait until command is processed or timeout occurs */
@@ -531,7 +532,7 @@ EXPORT_SYMBOL(nand_get_set_features_notsupp); 
 */

static int nand_wait(struct nand_chip *chip)

{



	struct mtd_info *mtd = nand_to_mtd(chip);

	unsigned long timeo = 400;

	u8 status;

	int ret;
@@ -546,9 +547,9 @@ static int nand_wait(struct nand_chip *chip) 
	if (ret)

		return ret;



	if (in_interrupt() || oops_in_progress)

	if (mtd->oops_panic_write) {

		panic_nand_wait(chip, timeo);

	else {

	} else {

		timeo = jiffies + msecs_to_jiffies(timeo);

		do {

			if (chip->legacy.dev_ready) {

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