Commit 875287ca authored by Linus Torvalds's avatar Linus Torvalds
Browse files
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: remove unecessary include of thread_info.h in entry.S
  m68knommu: enumerate INIT_THREAD fields properly
  headers_check fix: m68k, swab.h
  arch/m68knommu: Convert #ifdef DEBUG printk(KERN_DEBUG to pr_debug(
  m68knommu: remove obsolete reset code
  m68knommu: move CPU reset code for the 5272 ColdFire into its platform code
  m68knommu: move CPU reset code for the 528x ColdFire into its platform code
  m68knommu: move CPU reset code for the 527x ColdFire into its platform code
  m68knommu: move CPU reset code for the 523x ColdFire into its platform code
  m68knommu: move CPU reset code for the 520x ColdFire into its platform code
  m68knommu: add CPU reset code for the 532x ColdFire
  m68knommu: add CPU reset code for the 5249 ColdFire
  m68knommu: add CPU reset code for the 5206e ColdFire
  m68knommu: add CPU reset code for the 5206 ColdFire
  m68knommu: add CPU reset code for the 5407 ColdFire
  m68knommu: add CPU reset code for the 5307 ColdFire
  m68knommu: merge system reset for code ColdFire 523x family
  m68knommu: fix system reset for ColdFire 527x family
parents aee74f3b 193e9840
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+9 −0
Original line number Diff line number Diff line
@@ -59,5 +59,14 @@
#define MCFPIT_IMR		MCFINTC_IMRL
#define MCFPIT_IMR_IBIT		(1 << MCFINT_PIT1)

/*
 *  Reset Controll Unit.
 */
#define	MCF_RCR			0xFC0A0000
#define	MCF_RSR			0xFC0A0001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/****************************************************************************/
#endif  /* m520xsim_h */
+9 −0
Original line number Diff line number Diff line
@@ -41,5 +41,14 @@
#define	MCFSIM_DACR1		0x50		/* SDRAM base address 1 */
#define	MCFSIM_DMR1		0x54		/* SDRAM address mask 1 */

/*
 *  Reset Controll Unit (relative to IPSBAR).
 */
#define	MCF_RCR			0x110000
#define	MCF_RSR			0x110001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/****************************************************************************/
#endif	/* m523xsim_h */
+9 −0
Original line number Diff line number Diff line
@@ -70,5 +70,14 @@
#define UART2_ENABLE_MASK	0x3f00 
#endif

/*
 *  Reset Controll Unit (relative to IPSBAR).
 */
#define	MCF_RCR			0x110000
#define	MCF_RSR			0x110001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/****************************************************************************/
#endif	/* m527xsim_h */
+8 −0
Original line number Diff line number Diff line
@@ -56,6 +56,14 @@
#define MCF5282_INTC0_ICR17     (volatile u8 *) (MCF_IPSBAR + 0x0C51)


/*
 *  Reset Control Unit (relative to IPSBAR).
 */
#define	MCF_RCR			0x110000
#define	MCF_RSR			0x110001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/*********************************************************************
*
+12 −0
Original line number Diff line number Diff line
@@ -125,6 +125,18 @@
#define	ACR_CM_OFF_IMP		(3<<5)
#define	ACR_WPROTECT		(1<<2)

/*********************************************************************
 *
 * Reset Controller Module
 *
 *********************************************************************/

#define	MCF_RCR			0xFC0A0000
#define	MCF_RSR			0xFC0A0001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/*********************************************************************
 *
 * Inter-IC (I2C) Module
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