spi: lantiq: Add fifo size bit mask in SoC specific data structure (8743d215) · Commits · 戴 / test

drivers/spi/spi-lantiq-ssc.c

+9 −10

Original line number	Diff line number	Diff line
		@@ -58,9 +58,7 @@
		#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */

		#define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
		#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S)
		#define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
		#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S)
		#define LTQ_SPI_ID_MOD_S 8 /* Module ID */
		#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
		#define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */
		@@ -123,19 +121,15 @@
		LTQ_SPI_WHBSTATE_CLRTUE)

		#define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
		#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S)
		#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
		#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */

		#define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
		#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S)
		#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
		#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */

		#define LTQ_SPI_FSTAT_RXFFL_S 0
		#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S)
		#define LTQ_SPI_FSTAT_TXFFL_S 8
		#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S)

		#define LTQ_SPI_GPOCON_ISCSBN_S 8
		#define LTQ_SPI_GPOCON_INVOUTN_S 0
		@@ -161,6 +155,7 @@ struct lantiq_ssc_hwcfg {
		unsigned int irncr;
		unsigned int irnicr;
		bool irq_ack;
		u32 fifo_size_mask;
		};

		struct lantiq_ssc_spi {
		@@ -210,16 +205,18 @@ static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,

		static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
		{
		const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
		u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);

		return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
		return (fstat >> LTQ_SPI_FSTAT_TXFFL_S) & hwcfg->fifo_size_mask;
		}

		static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
		{
		const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
		u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);

		return fstat & LTQ_SPI_FSTAT_RXFFL_M;
		return (fstat >> LTQ_SPI_FSTAT_RXFFL_S) & hwcfg->fifo_size_mask;
		}

		static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
		@@ -807,6 +804,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
		.irnen_t = LTQ_SPI_IRNEN_T_XWAY,
		.irnicr = 0xF8,
		.irncr = 0xFC,
		.fifo_size_mask = GENMASK(5, 0),
		.irq_ack = false,
		};

		@@ -815,6 +813,7 @@ static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
		.irnen_t = LTQ_SPI_IRNEN_T_XRX,
		.irnicr = 0xF8,
		.irncr = 0xFC,
		.fifo_size_mask = GENMASK(5, 0),
		.irq_ack = false,
		};

		@@ -941,8 +940,8 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
		INIT_WORK(&spi->work, lantiq_ssc_bussy_work);

		id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
		spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
		spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
		spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask;
		spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask;
		supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
		revision = id & LTQ_SPI_ID_REV_M;

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