Commit 873c3319 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'stm32-dt-for-v5.10-1' of... 

Merge tag 'stm32-dt-for-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt

STM32 DT updates for v5.10, round 1

Highlights:
----------

MCU part:
 -Some changes on stm32h743: enable display controler, add SPI resets,
  use "st,stm32h7-uart" compatible.

MPU part:
 -Add new Odyssey SOM board based on STM32MP157CAC. It embeds 4GB eMMC, 512
  MB DDR3 RAM, USB and ETH connectors and a combo wifi/BT (AP6236 chip).
 -Add FMC2 EBI support on EV1 board.
 -Add arm-pmu node.
 -LXA:
  -Change ethernet phy delays to avoid kernel warnings.
  -Enable DDR50 eMMC mode.
 -DH:
  -Add new DH DRC02 unit board.
  -Add USB OTG support on PDK2 board.
  -Use uart8 RTS/CTS on PDK2 board.
  -Fix display PWM channel on PDK2 board.
  -Swap phy reset line and touchscreen irq on DHCOM SOM.
  -Drop QSPI CS2 on DHCOM SOM.
  -Update SDMMC pin config on AV96.
  -Enable uart7 RTS/CTS on AV96.

* tag 'stm32-dt-for-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: add arm-pmu node on stm32mp15
  ARM: dts: stm32: add FMC2 EBI support for stm32mp157c
  ARM: dts: stm32: lxa-mc1: enable DDR50 mode on eMMC
  ARM: dts: stm32: Fix DH PDK2 display PWM channel
  ARM: dts: stm32: Enable RTS/CTS for DH AV96 UART7
  ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOM
  ARM: dts: stm32: use stm32h7 usart compatible string for stm32h743
  ARM: dts: stm32: add resets property to spi device nodes on stm32h743
  ARM: dts: stm32: add display controller node to stm32h743
  ARM: dts: stm32: Enable RTS/CTS for DH PDK2 UART8
  ARM: dts: stm32: Drop QSPI CS2 pinmux on DHCOM
  ARM: dts: stm32: Add STM32MP1 UART8 RTS/CTS pinmux
  ARM: dts: stm32: add initial support for stm32mp157-odyssey board
  dt-bindings: arm: stm32: document Odyssey compatible
  dt-bindings: vendor-prefixes: add Seeed Studio
  ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delays
  ARM: dts: stm32: Add USB OTG support to DH PDK2
  ARM: dts: stm32: Fix sdmmc2 pins on AV96
  ARM: dts: stm32: Add DHSOM based DRC02 board
  ARM: dts: stm32: Move ethernet PHY into DH SoM DT

Link: https://lore.kernel.org/r/7e2a93c9-cf37-bc93-ed6e-d9cb1808b7a3@st.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents a1c259cd 71593c51

Documentation/devicetree/bindings/arm/stm32/stm32.yaml

+6 −0
Original line number Diff line number Diff line
@@ -50,4 +50,10 @@ properties: 
          - const: st,stm32mp157c-ev1

          - const: st,stm32mp157c-ed1

          - const: st,stm32mp157

      - description: Odyssey STM32MP1 SoM based Boards

        items:

              - enum:

                  - seeed,stm32mp157c-odyssey

              - const: seeed,stm32mp157c-odyssey-som

              - const: st,stm32mp157

...

Documentation/devicetree/bindings/vendor-prefixes.yaml

+2 −0
Original line number Diff line number Diff line
@@ -910,6 +910,8 @@ patternProperties: 
    description: Schindler

  "^seagate,.*":

    description: Seagate Technology PLC

  "^seeed,.*":

    description: Seeed Technology Co., Ltd

  "^seirobotics,.*":

    description: Shenzhen SEI Robotics Co., Ltd

  "^semtech,.*":

arch/arm/boot/dts/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -1055,6 +1055,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ 
	stm32746g-eval.dtb \

	stm32h743i-eval.dtb \

	stm32h743i-disco.dtb \

	stm32mp153c-dhcom-drc02.dtb \

	stm32mp157a-avenger96.dtb \

	stm32mp157a-dhcor-avenger96.dtb \

	stm32mp157a-dk1.dtb \
@@ -1064,7 +1065,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ 
	stm32mp157c-dk2.dtb \

	stm32mp157c-ed1.dtb \

	stm32mp157c-ev1.dtb \

	stm32mp157c-lxa-mc1.dtb

	stm32mp157c-lxa-mc1.dtb \

	stm32mp157c-odyssey.dtb

dtb-$(CONFIG_MACH_SUN4I) += \

	sun4i-a10-a1000.dtb \

	sun4i-a10-ba10-tvbox.dtb \

arch/arm/boot/dts/stm32h743.dtsi

+18 −2
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ 
			compatible = "st,stm32h7-spi";

			reg = <0x40003800 0x400>;

			interrupts = <36>;

			resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;

			clocks = <&rcc SPI2_CK>;

			status = "disabled";
@@ -121,12 +122,13 @@ 
			compatible = "st,stm32h7-spi";

			reg = <0x40003c00 0x400>;

			interrupts = <51>;

			resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;

			clocks = <&rcc SPI3_CK>;

			status = "disabled";

		};



		usart2: serial@40004400 {

			compatible = "st,stm32f7-uart";

			compatible = "st,stm32h7-uart";

			reg = <0x40004400 0x400>;

			interrupts = <38>;

			status = "disabled";
@@ -194,7 +196,7 @@ 
		};



		usart1: serial@40011000 {

			compatible = "st,stm32f7-uart";

			compatible = "st,stm32h7-uart";

			reg = <0x40011000 0x400>;

			interrupts = <37>;

			status = "disabled";
@@ -207,6 +209,7 @@ 
			compatible = "st,stm32h7-spi";

			reg = <0x40013000 0x400>;

			interrupts = <35>;

			resets = <&rcc STM32H7_APB2_RESET(SPI1)>;

			clocks = <&rcc SPI1_CK>;

			status = "disabled";

		};
@@ -217,6 +220,7 @@ 
			compatible = "st,stm32h7-spi";

			reg = <0x40013400 0x400>;

			interrupts = <84>;

			resets = <&rcc STM32H7_APB2_RESET(SPI4)>;

			clocks = <&rcc SPI4_CK>;

			status = "disabled";

		};
@@ -227,6 +231,7 @@ 
			compatible = "st,stm32h7-spi";

			reg = <0x40015000 0x400>;

			interrupts = <85>;

			resets = <&rcc STM32H7_APB2_RESET(SPI5)>;

			clocks = <&rcc SPI5_CK>;

			status = "disabled";

		};
@@ -329,6 +334,16 @@ 
			status = "disabled";

		};



		ltdc: display-controller@50001000 {

			compatible = "st,stm32-ltdc";

			reg = <0x50001000 0x200>;

			interrupts = <88>, <89>;

			resets = <&rcc STM32H7_APB3_RESET(LTDC)>;

			clocks = <&rcc LTDC_CK>;

			clock-names = "lcd";

			status = "disabled";

		};



		mdma1: dma-controller@52000000 {

			compatible = "st,stm32h7-mdma";

			reg = <0x52000000 0x1000>;
@@ -372,6 +387,7 @@ 
			compatible = "st,stm32h7-spi";

			reg = <0x58001400 0x400>;

			interrupts = <86>;

			resets = <&rcc STM32H7_APB4_RESET(SPI6)>;

			clocks = <&rcc SPI6_CK>;

			status = "disabled";

		};

arch/arm/boot/dts/stm32mp15-pinctrl.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -1437,6 +1437,24 @@ 
		};

	};



	sdmmc2_d47_pins_d: sdmmc2-d47-3 {

		pins {

			pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */

				 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */

				 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */

				 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */

		};

	};



	sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {

		pins {

			pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */

				 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */

				 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */

				 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */

		};

	};



	sdmmc3_b4_pins_a: sdmmc3-b4-0 {

		pins1 {

			pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@@ -1700,6 +1718,14 @@ 
		};

	};



	uart8_rtscts_pins_a: uart8rtscts-0 {

		pins {

			pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */

				 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */

			bias-disable;

		};

	};



	spi4_pins_a: spi4-0 {

		pins {

			pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */

CRA Git | Maintained and supported by SUSTech CRA and CCSE