Merge branch 'for-usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sarah/xhci (87367a0b) · Commits · 戴 / test

drivers/usb/host/ehci-pci.c

+39 −0

Original line number	Diff line number	Diff line
		@@ -348,11 +348,50 @@ static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
		return rc;
		}

		static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
		{
		return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
		pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == 0x1E26;
		}

		static void ehci_enable_xhci_companion(void)
		{
		struct pci_dev *companion = NULL;

		/* The xHCI and EHCI controllers are not on the same PCI slot */
		for_each_pci_dev(companion) {
		if (!usb_is_intel_switchable_xhci(companion))
		continue;
		usb_enable_xhci_ports(companion);
		return;
		}
		}

		static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
		{
		struct ehci_hcd *ehci = hcd_to_ehci(hcd);
		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);

		/* The BIOS on systems with the Intel Panther Point chipset may or may
		* not support xHCI natively. That means that during system resume, it
		* may switch the ports back to EHCI so that users can use their
		* keyboard to select a kernel from GRUB after resume from hibernate.
		*
		* The BIOS is supposed to remember whether the OS had xHCI ports
		* enabled before resume, and switch the ports back to xHCI when the
		* BIOS/OS semaphore is written, but we all know we can't trust BIOS
		* writers.
		*
		* Unconditionally switch the ports back to xHCI after a system resume.
		* We can't tell whether the EHCI or xHCI controller will be resumed
		* first, so we have to do the port switchover in both drivers. Writing
		* a '1' to the port switchover registers should have no effect if the
		* port was already switched over.
		*/
		if (usb_is_intel_switchable_ehci(pdev))
		ehci_enable_xhci_companion();

		// maybe restore FLADJ

		if (time_before(jiffies, ehci->next_statechange))

drivers/usb/host/pci-quirks.c

+63 −0

Original line number	Diff line number	Diff line
		@@ -69,6 +69,9 @@
		#define NB_PIF0_PWRDOWN_0 0x01100012
		#define NB_PIF0_PWRDOWN_1 0x01100013

		#define USB_INTEL_XUSB2PR 0xD0
		#define USB_INTEL_USB3_PSSEN 0xD8

		static struct amd_chipset_info {
		struct pci_dev *nb_dev;
		struct pci_dev *smbus_dev;
		@@ -673,6 +676,64 @@ static int handshake(void __iomem *ptr, u32 mask, u32 done,
		return -ETIMEDOUT;
		}

		bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
		{
		return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
		pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
		}
		EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);

		/*
		* Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
		* share some number of ports. These ports can be switched between either
		* controller. Not all of the ports under the EHCI host controller may be
		* switchable.
		*
		* The ports should be switched over to xHCI before PCI probes for any device
		* start. This avoids active devices under EHCI being disconnected during the
		* port switchover, which could cause loss of data on USB storage devices, or
		* failed boot when the root file system is on a USB mass storage device and is
		* enumerated under EHCI first.
		*
		* We write into the xHC's PCI configuration space in some Intel-specific
		* registers to switch the ports over. The USB 3.0 terminations and the USB
		* 2.0 data wires are switched separately. We want to enable the SuperSpeed
		* terminations before switching the USB 2.0 wires over, so that USB 3.0
		* devices connect at SuperSpeed, rather than at USB 2.0 speeds.
		*/
		void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
		{
		u32 ports_available;

		ports_available = 0xffffffff;
		/* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
		* Register, to turn on SuperSpeed terminations for all
		* available ports.
		*/
		pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
		cpu_to_le32(ports_available));

		pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
		&ports_available);
		dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
		"under xHCI: 0x%x\n", ports_available);

		ports_available = 0xffffffff;
		/* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
		* switch the USB 2.0 power and data lines over to the xHCI
		* host.
		*/
		pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
		cpu_to_le32(ports_available));

		pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
		&ports_available);
		dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
		"to xHCI: 0x%x\n", ports_available);
		}
		EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);

		/**
		* PCI Quirks for xHCI.
		*
		@@ -732,6 +793,8 @@ static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
		writel(XHCI_LEGACY_DISABLE_SMI,
		base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);

		if (usb_is_intel_switchable_xhci(pdev))
		usb_enable_xhci_ports(pdev);
		hc_init:
		op_reg_base = base + XHCI_HC_LENGTH(readl(base));

drivers/usb/host/pci-quirks.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -8,6 +8,8 @@ int usb_amd_find_chipset_info(void);
		void usb_amd_dev_put(void);
		void usb_amd_quirk_pll_disable(void);
		void usb_amd_quirk_pll_enable(void);
		bool usb_is_intel_switchable_xhci(struct pci_dev *pdev);
		void usb_enable_xhci_ports(struct pci_dev *xhci_pdev);
		#else
		static inline void usb_amd_quirk_pll_disable(void) {}
		static inline void usb_amd_quirk_pll_enable(void) {}

drivers/usb/host/xhci-pci.c

+26 −0

Original line number	Diff line number	Diff line
		@@ -118,6 +118,12 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
		/* AMD PLL quirk */
		if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks \|= XHCI_AMD_PLL_FIX;
		if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks \|= XHCI_SPURIOUS_SUCCESS;
		xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		}

		/* Make sure the HC is halted. */
		retval = xhci_halt(xhci);
		@@ -242,8 +248,28 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
		static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
		{
		struct xhci_hcd *xhci = hcd_to_xhci(hcd);
		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
		int retval = 0;

		/* The BIOS on systems with the Intel Panther Point chipset may or may
		* not support xHCI natively. That means that during system resume, it
		* may switch the ports back to EHCI so that users can use their
		* keyboard to select a kernel from GRUB after resume from hibernate.
		*
		* The BIOS is supposed to remember whether the OS had xHCI ports
		* enabled before resume, and switch the ports back to xHCI when the
		* BIOS/OS semaphore is written, but we all know we can't trust BIOS
		* writers.
		*
		* Unconditionally switch the ports back to xHCI after a system resume.
		* We can't tell whether the EHCI or xHCI controller will be resumed
		* first, so we have to do the port switchover in both drivers. Writing
		* a '1' to the port switchover registers should have no effect if the
		* port was already switched over.
		*/
		if (usb_is_intel_switchable_xhci(pdev))
		usb_enable_xhci_ports(pdev);

		retval = xhci_resume(xhci, hibernated);
		return retval;
		}

drivers/usb/host/xhci-ring.c

+37 −52

Original line number	Diff line number	Diff line
		@@ -167,12 +167,6 @@ static void inc_deq(struct xhci_hcd xhci, struct xhci_ring ring, bool consumer
		next = ring->dequeue;
		}
		addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
		if (ring == xhci->event_ring)
		xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
		else if (ring == xhci->cmd_ring)
		xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
		else
		xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
		}

		/*
		@@ -248,12 +242,6 @@ static void inc_enq(struct xhci_hcd xhci, struct xhci_ring ring,
		next = ring->enqueue;
		}
		addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
		if (ring == xhci->event_ring)
		xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
		else if (ring == xhci->cmd_ring)
		xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
		else
		xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
		}

		/*
		@@ -636,13 +624,11 @@ static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
		}
		}
		usb_hcd_unlink_urb_from_ep(hcd, urb);
		xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);

		spin_unlock(&xhci->lock);
		usb_hcd_giveback_urb(hcd, urb, status);
		xhci_urb_free_priv(xhci, urb_priv);
		spin_lock(&xhci->lock);
		xhci_dbg(xhci, "%s URB given back\n", adjective);
		}
		}

		@@ -692,6 +678,8 @@ static void handle_stopped_endpoint(struct xhci_hcd *xhci,

		if (list_empty(&ep->cancelled_td_list)) {
		xhci_stop_watchdog_timer_in_irq(xhci, ep);
		ep->stopped_td = NULL;
		ep->stopped_trb = NULL;
		ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
		return;
		}
		@@ -1093,8 +1081,13 @@ static void handle_cmd_completion(struct xhci_hcd *xhci,
		complete(&xhci->addr_dev);
		break;
		case TRB_TYPE(TRB_DISABLE_SLOT):
		if (xhci->devs[slot_id])
		if (xhci->devs[slot_id]) {
		if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
		/* Delete default control endpoint resources */
		xhci_free_device_endpoint_resources(xhci,
		xhci->devs[slot_id], true);
		xhci_free_virt_device(xhci, slot_id);
		}
		break;
		case TRB_TYPE(TRB_CONFIG_EP):
		virt_dev = xhci->devs[slot_id];
		@@ -1630,7 +1623,6 @@ static int process_ctrl_td(struct xhci_hcd xhci, struct xhci_td td,
		"without IOC set??\n");
		*status = -ESHUTDOWN;
		} else {
		xhci_dbg(xhci, "Successful control transfer!\n");
		*status = 0;
		}
		break;
		@@ -1727,7 +1719,6 @@ static int process_isoc_td(struct xhci_hcd xhci, struct xhci_td td,
		switch (trb_comp_code) {
		case COMP_SUCCESS:
		frame->status = 0;
		xhci_dbg(xhci, "Successful isoc transfer!\n");
		break;
		case COMP_SHORT_TX:
		frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
		@@ -1837,12 +1828,6 @@ static int process_bulk_intr_td(struct xhci_hcd xhci, struct xhci_td td,
		else
		*status = 0;
		} else {
		if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
		xhci_dbg(xhci, "Successful bulk "
		"transfer!\n");
		else
		xhci_dbg(xhci, "Successful interrupt "
		"transfer!\n");
		*status = 0;
		}
		break;
		@@ -1856,6 +1841,7 @@ static int process_bulk_intr_td(struct xhci_hcd xhci, struct xhci_td td,
		/* Others already handled above */
		break;
		}
		if (trb_comp_code == COMP_SHORT_TX)
		xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
		"%d bytes untransferred\n",
		td->urb->ep->desc.bEndpointAddress,
		@@ -1954,7 +1940,6 @@ static int handle_tx_event(struct xhci_hcd *xhci,

		/* Endpoint ID is 1 based, our index is zero based */
		ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
		xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
		ep = &xdev->eps[ep_index];
		ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
		ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
		@@ -2081,6 +2066,16 @@ static int handle_tx_event(struct xhci_hcd *xhci,
		if (!event_seg) {
		if (!ep->skip \|\|
		!usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
		/* Some host controllers give a spurious
		* successful event after a short transfer.
		* Ignore it.
		*/
		if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
		ep_ring->last_td_was_short) {
		ep_ring->last_td_was_short = false;
		ret = 0;
		goto cleanup;
		}
		/* HC is busted, give up! */
		xhci_err(xhci,
		"ERROR Transfer event TRB DMA ptr not "
		@@ -2091,6 +2086,10 @@ static int handle_tx_event(struct xhci_hcd *xhci,
		ret = skip_isoc_td(xhci, td, event, ep, &status);
		goto cleanup;
		}
		if (trb_comp_code == COMP_SHORT_TX)
		ep_ring->last_td_was_short = true;
		else
		ep_ring->last_td_was_short = false;

		if (ep->skip) {
		xhci_dbg(xhci, "Found td. Clear skip flag.\n");
		@@ -2149,9 +2148,15 @@ cleanup:
		xhci_urb_free_priv(xhci, urb_priv);

		usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
		if ((urb->actual_length != urb->transfer_buffer_length &&
		(urb->transfer_flags &
		URB_SHORT_NOT_OK)) \|\|
		status != 0)
		xhci_dbg(xhci, "Giveback URB %p, len = %d, "
		"status = %d\n",
		urb, urb->actual_length, status);
		"expected = %x, status = %d\n",
		urb, urb->actual_length,
		urb->transfer_buffer_length,
		status);
		spin_unlock(&xhci->lock);
		usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
		spin_lock(&xhci->lock);
		@@ -2180,7 +2185,6 @@ static int xhci_handle_event(struct xhci_hcd *xhci)
		int update_ptrs = 1;
		int ret;

		xhci_dbg(xhci, "In %s\n", __func__);
		if (!xhci->event_ring \|\| !xhci->event_ring->dequeue) {
		xhci->error_bitmask \|= 1 << 1;
		return 0;
		@@ -2193,7 +2197,6 @@ static int xhci_handle_event(struct xhci_hcd *xhci)
		xhci->error_bitmask \|= 1 << 2;
		return 0;
		}
		xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);

		/*
		* Barrier between reading the TRB_CYCLE (valid) flag above and any
		@@ -2203,20 +2206,14 @@ static int xhci_handle_event(struct xhci_hcd *xhci)
		/* FIXME: Handle more event types. */
		switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
		case TRB_TYPE(TRB_COMPLETION):
		xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
		handle_cmd_completion(xhci, &event->event_cmd);
		xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
		break;
		case TRB_TYPE(TRB_PORT_STATUS):
		xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
		handle_port_status(xhci, event);
		xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
		update_ptrs = 0;
		break;
		case TRB_TYPE(TRB_TRANSFER):
		xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
		ret = handle_tx_event(xhci, &event->trans_event);
		xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
		if (ret < 0)
		xhci->error_bitmask \|= 1 << 9;
		else
		@@ -2273,16 +2270,6 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd)
		spin_unlock(&xhci->lock);
		return IRQ_NONE;
		}
		xhci_dbg(xhci, "op reg status = %08x\n", status);
		xhci_dbg(xhci, "Event ring dequeue ptr:\n");
		xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
		(unsigned long long)
		xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
		lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
		upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
		(unsigned int) le32_to_cpu(trb->link.intr_target),
		(unsigned int) le32_to_cpu(trb->link.control));

		if (status & STS_FATAL) {
		xhci_warn(xhci, "WARNING: Host System Error\n");
		xhci_halt(xhci);
		@@ -2397,7 +2384,6 @@ static int prepare_ring(struct xhci_hcd xhci, struct xhci_ring ep_ring,
		u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
		{
		/* Make sure the endpoint has been added to xHC schedule */
		xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
		switch (ep_state) {
		case EP_STATE_DISABLED:
		/*
		@@ -2434,7 +2420,6 @@ static int prepare_ring(struct xhci_hcd xhci, struct xhci_ring ep_ring,
		struct xhci_ring *ring = ep_ring;
		union xhci_trb *next;

		xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
		next = ring->enqueue;

		while (last_trb(xhci, ring, ring->enq_seg, next)) {

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