Merge branch 'for-upstream/juno-pcie' of git://linux-arm.org/linux-ld into next/arm64 (8713181d) · Commits · 戴 / test

Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt

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		* ARM Juno R1 PCIe interface

		This PCIe host controller is based on PLDA XpressRICH3-AXI IP
		and thus inherits all the common properties defined in plda,xpressrich3-axi.txt
		as well as the base properties defined in host-generic-pci.txt.

		Required properties:
		- compatible: "arm,juno-r1-pcie"
		- dma-coherent: The host controller bridges the AXI transactions into PCIe bus
		in a manner that makes the DMA operations to appear coherent to the CPUs.

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		* PLDA XpressRICH3-AXI host controller

		The PLDA XpressRICH3-AXI host controller can be configured in a manner that
		makes it compliant with the SBSA[1] standard published by ARM Ltd. For those
		scenarios, the host-generic-pci.txt bindings apply with the following additions
		to the compatible property:

		Required properties:
		- compatible: should contain "plda,xpressrich3-axi" to identify the IP used.


		[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/

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		@@ -168,6 +168,7 @@ pericom Pericom Technology Inc.
		phytec PHYTEC Messtechnik GmbH
		picochip Picochip Ltd
		plathome Plat'Home Co., Ltd.
		plda PLDA
		pixcir PIXCIR MICROELECTRONICS Co., Ltd
		powervr PowerVR (deprecated, use img)
		qca Qualcomm Atheros, Inc.

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		@@ -109,6 +109,26 @@

		#include "juno-base.dtsi"

		pcie-controller@40000000 {
		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
		device_type = "pci";
		reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
		bus-range = <0 255>;
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		dma-coherent;
		ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
		<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
		<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
		<0 0 0 2 &gic 0 0 0 137 4>,
		<0 0 0 3 &gic 0 0 0 138 4>,
		<0 0 0 4 &gic 0 0 0 139 4>;
		msi-parent = <&v2m_0>;
		};
		};

		&memtimer {

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