net: phy: dp83867: Set FORCE_LINK_GOOD to default after reset (86ffe920) · Commits · 戴 / test

According to the Datasheet this bit should be 0 (Normal operation) in default. With the FORCE_LINK_GOOD bit set, it is not possible to get a link. This patch sets FORCE_LINK_GOOD to the default value after resetting the phy. Signed-off-by:

Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by:

Andrew Lunn <andrew@lunn.ch> Signed-off-by:

David S. Miller <davem@davemloft.net>

drivers/net/phy/dp83867.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -97,6 +97,7 @@
		#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
		#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
		#define DP83867_PHYCR_RESERVED_MASK BIT(11)
		#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)

		/* RGMIIDCTL bits */
		#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
		@@ -599,7 +600,12 @@ static int dp83867_phy_reset(struct phy_device *phydev)

		usleep_range(10, 20);

		return 0;
		/* After reset FORCE_LINK_GOOD bit is set. Although the
		* default value should be unset. Disable FORCE_LINK_GOOD
		* for the phy to work properly.
		*/
		return phy_modify(phydev, MII_DP83867_PHYCTRL,
		DP83867_PHYCR_FORCE_LINK_GOOD, 0);
		}

		static struct phy_driver dp83867_driver[] = {

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