Merge tag 'omap-for-v3.10/gpmc-signed' of...

Timing properties for child nodes. All are optional and default to 0.

 - gpmc,sync-clk:	Minimum clock period for synchronous mode, in picoseconds

 Chip-select signal timings corresponding to GPMC_CONFIG2:

 - gpmc,cs-on:		Assertion time

 - gpmc,cs-rd-off:	Read deassertion time

 - gpmc,cs-wr-off:	Write deassertion time

 ADV signal timings corresponding to GPMC_CONFIG3:

 - gpmc,adv-on:		Assertion time

 - gpmc,adv-rd-off:	Read deassertion time

 - gpmc,adv-wr-off:	Write deassertion time

 WE signals timings corresponding to GPMC_CONFIG4:

 - gpmc,we-on:		Assertion time

 - gpmc,we-off:		Deassertion time

 OE signals timings corresponding to GPMC_CONFIG4:

 - gpmc,oe-on:		Assertion time

 - gpmc,oe-off:		Deassertion time

 Access time and cycle time timings corresponding to GPMC_CONFIG5:

 - gpmc,page-burst-access: Multiple access word delay

 - gpmc,access:		Start-cycle to first data valid delay

 - gpmc,rd-cycle:	Total read cycle time

 - gpmc,wr-cycle:	Total write cycle time

 - gpmc,sync-clk-ps:	Minimum clock period for synchronous mode, in picoseconds

 Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:

 - gpmc,cs-on-ns:	Assertion time

 - gpmc,cs-rd-off-ns:	Read deassertion time

 - gpmc,cs-wr-off-ns:	Write deassertion time

 ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:

 - gpmc,adv-on-ns:	Assertion time

 - gpmc,adv-rd-off-ns:	Read deassertion time

 - gpmc,adv-wr-off-ns:	Write deassertion time

 WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:

 - gpmc,we-on-ns	Assertion time

 - gpmc,we-off-ns:	Deassertion time

 OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:

 - gpmc,oe-on-ns:	Assertion time

 - gpmc,oe-off-ns:	Deassertion time

 Access time and cycle time timings (in nanoseconds) corresponding to

 GPMC_CONFIG5:

 - gpmc,page-burst-access-ns: 	Multiple access word delay

 - gpmc,access-ns:		Start-cycle to first data valid delay

 - gpmc,rd-cycle-ns:		Total read cycle time

 - gpmc,wr-cycle-ns:		Total write cycle time

 - gpmc,bus-turnaround-ns:	Turn-around time between successive accesses

 - gpmc,cycle2cycle-delay-ns:	Delay between chip-select pulses

 - gpmc,clk-activation-ns: 	GPMC clock activation time

 - gpmc,wait-monitoring-ns:	Start of wait monitoring with regard to valid

				data

Boolean timing parameters. If property is present parameter enabled and

disabled if omitted:

 - gpmc,adv-extra-delay:	ADV signal is delayed by half GPMC clock

 - gpmc,cs-extra-delay:		CS signal is delayed by half GPMC clock

 - gpmc,cycle2cycle-diffcsen:	Add "cycle2cycle-delay" between successive

				accesses to a different CS

 - gpmc,cycle2cycle-samecsen:	Add "cycle2cycle-delay" between successive

				accesses to the same CS

 - gpmc,oe-extra-delay:		OE signal is delayed by half GPMC clock

 - gpmc,we-extra-delay:		WE signal is delayed by half GPMC clock

 - gpmc,time-para-granularity:	Multiply all access times by 2

The following are only applicable to OMAP3+ and AM335x:

 - gpmc,wr-access

 - gpmc,wr-data-mux-bus

 - gpmc,wr-access-ns:		In synchronous write mode, for single or

				burst accesses, defines the number of

				GPMC_FCLK cycles from start access time

				to the GPMC_CLK rising edge used by the

				memory device for the first data capture.

 - gpmc,wr-data-mux-bus-ns:	In address-data multiplex mode, specifies

				the time when the first data is driven on

				the address-data bus.

GPMC chip-select settings properties for child nodes. All are optional.

- gpmc,burst-length	Page/burst length. Must be 4, 8 or 16.

- gpmc,burst-wrap	Enables wrap bursting

- gpmc,burst-read	Enables read page/burst mode

- gpmc,burst-write	Enables write page/burst mode

- gpmc,device-nand	Device is NAND

- gpmc,device-width	Total width of device(s) connected to a GPMC

			chip-select in bytes. The GPMC supports 8-bit

			and 16-bit devices and so this property must be

			1 or 2.

- gpmc,mux-add-data	Address and data multiplexing configuration.

			Valid values are 1 for address-address-data

			multiplexing mode and 2 for address-data

			multiplexing mode.

- gpmc,sync-read	Enables synchronous read. Defaults to asynchronous

			is this is not set.

- gpmc,sync-write	Enables synchronous writes. Defaults to asynchronous

			is this is not set.

- gpmc,wait-pin		Wait-pin used by client. Must be less than

			"gpmc,num-waitpins".

- gpmc,wait-on-read	Enables wait monitoring on reads.

- gpmc,wait-on-write	Enables wait monitoring on writes.

Example for an AM33xx board:

Device tree bindings for NOR flash connect to TI GPMC

NOR flash connected to the TI GPMC (found on OMAP boards) are represented as

child nodes of the GPMC controller with a name of "nor".

All timing relevant properties as well as generic GPMC child properties are

explained in a separate documents. Please refer to

Documentation/devicetree/bindings/bus/ti-gpmc.txt

Required properties:

- bank-width: 		Width of NOR flash in bytes. GPMC supports 8-bit and

			16-bit devices and so must be either 1 or 2 bytes.

- compatible:		Documentation/devicetree/bindings/mtd/mtd-physmap.txt

- gpmc,cs-on-ns:		Chip-select assertion time

- gpmc,cs-rd-off-ns:	Chip-select de-assertion time for reads

- gpmc,cs-wr-off-ns:	Chip-select de-assertion time for writes

- gpmc,oe-on-ns:	Output-enable assertion time

- gpmc,oe-off-ns:	Output-enable de-assertion time

- gpmc,we-on-ns		Write-enable assertion time

- gpmc,we-off-ns:	Write-enable de-assertion time

- gpmc,access-ns:	Start cycle to first data capture (read access)

- gpmc,rd-cycle-ns:	Total read cycle time

- gpmc,wr-cycle-ns:	Total write cycle time

- linux,mtd-name:	Documentation/devicetree/bindings/mtd/mtd-physmap.txt

- reg:			Chip-select, base address (relative to chip-select)

			and size of NOR flash. Note that base address will be

			typically 0 as this is the start of the chip-select.

Optional properties:

- gpmc,XXX		Additional GPMC timings and settings parameters. See

			Documentation/devicetree/bindings/bus/ti-gpmc.txt

Optional properties for partiton table parsing:

- #address-cells: should be set to 1

- #size-cells: should be set to 1

Example:

gpmc: gpmc@6e000000 {

	compatible = "ti,omap3430-gpmc", "simple-bus";

	ti,hwmods = "gpmc";

	reg = <0x6e000000 0x1000>;

	interrupts = <20>;

	gpmc,num-cs = <8>;

	gpmc,num-waitpins = <4>;

	#address-cells = <2>;

	#size-cells = <1>;

	ranges = <0 0 0x10000000 0x08000000>;

	nor@0,0 {

		compatible = "cfi-flash";

		linux,mtd-name= "intel,pf48f6000m0y1be";

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0 0 0x08000000>;

		bank-width = <2>;

		gpmc,mux-add-data;

		gpmc,cs-on-ns = <0>;

		gpmc,cs-rd-off-ns = <186>;

		gpmc,cs-wr-off-ns = <186>;

		gpmc,adv-on-ns = <12>;

		gpmc,adv-rd-off-ns = <48>;

		gpmc,adv-wr-off-ns = <48>;

		gpmc,oe-on-ns = <54>;

		gpmc,oe-off-ns = <168>;

		gpmc,we-on-ns = <54>;

		gpmc,we-off-ns = <168>;

		gpmc,rd-cycle-ns = <186>;

		gpmc,wr-cycle-ns = <186>;

		gpmc,access-ns = <114>;

		gpmc,page-burst-access-ns = <6>;

		gpmc,bus-turnaround-ns = <12>;

		gpmc,cycle2cycle-delay-ns = <18>;

		gpmc,wr-data-mux-bus-ns = <90>;

		gpmc,wr-access-ns = <186>;

		gpmc,cycle2cycle-samecsen;

		gpmc,cycle2cycle-diffcsen;

		partition@0 {

			label = "bootloader-nor";

			reg = <0 0x40000>;

		};

		partition@0x40000 {

			label = "params-nor";

			reg = <0x40000 0x40000>;

		};

		partition@0x80000 {

			label = "kernel-nor";

			reg = <0x80000 0x200000>;

		};

		partition@0x280000 {

			label = "filesystem-nor";

			reg = <0x240000 0x7d80000>;

		};

	};

};

Required properties:

 - reg:			The CS line the peripheral is connected to

 - gpmc,device-width	Width of the ONENAND device connected to the GPMC

			in bytes. Must be 1 or 2.

Optional properties:

		onenand@0 {

			reg = <0 0 0>; /* CS0, offset 0 */

			gpmc,device-width = <2>;

			#address-cells = <1>;

			#size-cells = <1>;

Device tree bindings for Ethernet chip connected to TI GPMC

Besides being used to interface with external memory devices, the

General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices

such as ethernet controllers to processors using the TI GPMC as a data bus.

Ethernet controllers connected to TI GPMC are represented as child nodes of

the GPMC controller with an "ethernet" name.

All timing relevant properties as well as generic GPMC child properties are

explained in a separate documents. Please refer to

Documentation/devicetree/bindings/bus/ti-gpmc.txt

For the properties relevant to the ethernet controller connected to the GPMC

refer to the binding documentation of the device. For example, the documentation

for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt

Child nodes need to specify the GPMC bus address width using the "bank-width"

property but is possible that an ethernet controller also has a property to

specify the I/O registers address width. Even when the GPMC has a maximum 16-bit

address width, it supports devices with 32-bit word registers.

For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an

OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".

Required properties:

- bank-width: 		Address width of the device in bytes. GPMC supports 8-bit

			and 16-bit devices and so must be either 1 or 2 bytes.

- compatible:		Compatible string property for the ethernet child device.

- gpmc,cs-on:		Chip-select assertion time

- gpmc,cs-rd-off:	Chip-select de-assertion time for reads

- gpmc,cs-wr-off:	Chip-select de-assertion time for writes

- gpmc,oe-on:		Output-enable assertion time

- gpmc,oe-off		Output-enable de-assertion time

- gpmc,we-on:		Write-enable assertion time

- gpmc,we-off:		Write-enable de-assertion time

- gpmc,access:		Start cycle to first data capture (read access)

- gpmc,rd-cycle:	Total read cycle time

- gpmc,wr-cycle:	Total write cycle time

- reg:			Chip-select, base address (relative to chip-select)

			and size of the memory mapped for the device.

			Note that base address will be typically 0 as this

			is the start of the chip-select.

Optional properties:

- gpmc,XXX		Additional GPMC timings and settings parameters. See

			Documentation/devicetree/bindings/bus/ti-gpmc.txt

Example:

gpmc: gpmc@6e000000 {

	compatible = "ti,omap3430-gpmc";

	ti,hwmods = "gpmc";

	reg = <0x6e000000 0x1000>;

	interrupts = <20>;

	gpmc,num-cs = <8>;

	gpmc,num-waitpins = <4>;

	#address-cells = <2>;

	#size-cells = <1>;

	ranges = <5 0 0x2c000000 0x1000000>;

	ethernet@5,0 {

		compatible = "smsc,lan9221", "smsc,lan9115";

		reg = <5 0 0xff>;

		bank-width = <2>;

		gpmc,mux-add-data;

		gpmc,cs-on = <0>;

		gpmc,cs-rd-off = <186>;

		gpmc,cs-wr-off = <186>;

		gpmc,adv-on = <12>;

		gpmc,adv-rd-off = <48>;

		gpmc,adv-wr-off = <48>;

		gpmc,oe-on = <54>;

		gpmc,oe-off = <168>;

		gpmc,we-on = <54>;

		gpmc,we-off = <168>;

		gpmc,rd-cycle = <186>;

		gpmc,wr-cycle = <186>;

		gpmc,access = <114>;

		gpmc,page-burst-access = <6>;

		gpmc,bus-turnaround = <12>;

		gpmc,cycle2cycle-delay = <18>;

		gpmc,wr-data-mux-bus = <90>;

		gpmc,wr-access = <186>;

		gpmc,cycle2cycle-samecsen;

		gpmc,cycle2cycle-diffcsen;

		interrupt-parent = <&gpio6>;

		interrupts = <16>;

		vmmc-supply = <&vddvario>;

		vmmc_aux-supply = <&vdd33a>;

		reg-io-width = <4>;

		smsc,save-mac-address;

	};

};

	t.cs_wr_off = gpmc_t->cs_wr_off;

	t.wr_cycle = gpmc_t->wr_cycle;

	/* Configure GPMC */

	if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)

		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);

	else

		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);

	gpmc_cs_configure(gpmc_nand_data->cs,

			GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);

	gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);

	err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);

	if (err)

		return err;

		   struct gpmc_timings *gpmc_t)

{

	int err	= 0;

	struct gpmc_settings s;

	struct device *dev = &gpmc_nand_device.dev;

	memset(&s, 0, sizeof(struct gpmc_settings));

	gpmc_nand_device.dev.platform_data = gpmc_nand_data;

	err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,

				(unsigned long *)&gpmc_nand_resource[0].start);

	if (err < 0) {

		dev_err(dev, "Cannot request GPMC CS\n");

		dev_err(dev, "Cannot request GPMC CS %d, error %d\n",

			gpmc_nand_data->cs, err);

		return err;

	}

			dev_err(dev, "Unable to set gpmc timings: %d\n", err);

			return err;

		}

	}

		if (gpmc_nand_data->of_node) {

			gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);

		} else {

			s.device_nand = true;

			/* Enable RD PIN Monitoring Reg */

			if (gpmc_nand_data->dev_ready) {

		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);

				s.wait_on_read = true;

				s.wait_on_write = true;

			}

		}

		if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)

			s.device_width = GPMC_DEVWIDTH_16BIT;

		else

			s.device_width = GPMC_DEVWIDTH_8BIT;

		err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);

		if (err < 0)

			goto out_free_cs;

		err = gpmc_configure(GPMC_CONFIG_WP, 0);

		if (err < 0)

			goto out_free_cs;

	}

	gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);