Commit 86f93c93 authored by Amit Kucheria's avatar Amit Kucheria Committed by Andy Gross
Browse files

arm64: dts: msm8998: efficiency is not valid property 



efficiency comes from downstream. The valid upstream property is
capacity-dmips-mhz but until we can come up with those numbers, remove
this property.

Signed-off-by: default avatarAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: default avatarAndy Gross <agross@kernel.org>
parent 50325048

arch/arm64/boot/dts/qcom/msm8998.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -78,7 +78,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";
@@ -97,7 +96,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";
@@ -112,7 +110,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";
@@ -127,7 +124,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";
@@ -142,7 +138,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			efficiency = <1536>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

				compatible = "arm,arch-cache";
@@ -161,7 +156,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x101>;

			enable-method = "psci";

			efficiency = <1536>;

			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";
@@ -176,7 +170,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x102>;

			enable-method = "psci";

			efficiency = <1536>;

			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";
@@ -191,7 +184,6 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x103>;

			enable-method = "psci";

			efficiency = <1536>;

			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";

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