Commit 86e81794 authored by Chinh T Cao's avatar Chinh T Cao Committed by Jeff Kirsher
Browse files

ice: Create a generic name for the ice_rx_flg64_bits structure 



This structure is used to define the packet flags. These flags are
applicable for both TX and RX packet. Thus, this patch changes its
name from ice_rx_flag64_bits to ice_flg64_bits, and its member definition.

Signed-off-by: default avatarChinh T Cao <chinh.t.cao@intel.com>
Reviewed-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 2bdc97be

drivers/net/ethernet/intel/ice/ice_common.c

+13 −13
Original line number Diff line number Diff line
@@ -358,22 +358,22 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id) 
	 */

	case ICE_RXDID_FLEX_NIC:

	case ICE_RXDID_FLEX_NIC_2:

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG,

				   ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI,

				   ICE_RXFLG_FIN, idx++);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,

				   ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,

				   ICE_FLG_FIN, idx++);

		/* flex flag 1 is not used for flexi-flag programming, skipping

		 * these four FLG64 bits.

		 */

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST,

				   ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI,

				   ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100,

				   ICE_RXFLG_EVLAN_x9100, idx++);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100,

				   ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC,

				   ICE_RXFLG_TNL0, idx++);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,

				   ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,

				   ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,

				   ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,

				   ICE_FLG_EVLAN_x9100, idx++);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,

				   ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,

				   ICE_FLG_TNL0, idx++);

		ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,

				   ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);

		break;



	default:

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

+17 −17
Original line number Diff line number Diff line
@@ -208,23 +208,23 @@ enum ice_flex_rx_mdid { 
	ICE_RX_MDID_HASH_HIGH,

};



/* Rx Flag64 packet flag bits */

enum ice_rx_flg64_bits {

	ICE_RXFLG_PKT_DSI	= 0,

	ICE_RXFLG_EVLAN_x8100	= 15,

	ICE_RXFLG_EVLAN_x9100,

	ICE_RXFLG_VLAN_x8100,

	ICE_RXFLG_TNL_MAC	= 22,

	ICE_RXFLG_TNL_VLAN,

	ICE_RXFLG_PKT_FRG,

	ICE_RXFLG_FIN		= 32,

	ICE_RXFLG_SYN,

	ICE_RXFLG_RST,

	ICE_RXFLG_TNL0		= 38,

	ICE_RXFLG_TNL1,

	ICE_RXFLG_TNL2,

	ICE_RXFLG_UDP_GRE,

	ICE_RXFLG_RSVD		= 63

/* RX/TX Flag64 packet flag bits */

enum ice_flg64_bits {

	ICE_FLG_PKT_DSI		= 0,

	ICE_FLG_EVLAN_x8100	= 15,

	ICE_FLG_EVLAN_x9100,

	ICE_FLG_VLAN_x8100,

	ICE_FLG_TNL_MAC		= 22,

	ICE_FLG_TNL_VLAN,

	ICE_FLG_PKT_FRG,

	ICE_FLG_FIN		= 32,

	ICE_FLG_SYN,

	ICE_FLG_RST,

	ICE_FLG_TNL0		= 38,

	ICE_FLG_TNL1,

	ICE_FLG_TNL2,

	ICE_FLG_UDP_GRE,

	ICE_FLG_RSVD		= 63

};



/* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */

CRA Git | Maintained and supported by SUSTech CRA and CCSE