Commit 86d0b6a1 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/dt' 

  - Add common schema for PCI endpoint controllers (Kishon Vijay Abraham I)

  - Add host and endpoint schemas for Cadence PCIe core (Kishon Vijay
    Abraham I)

  - Convert Cadence platform bindings to DT schema (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/dt:
  dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema
  dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe
  dt-bindings: PCI: Add PCI Endpoint Controller Schema
parents d620d864 11be8af7

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt

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* Cadence PCIe endpoint controller



Required properties:

- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.

- reg: Should contain the controller register base address and AXI interface

  region base address respectively.

- reg-names: Must be "reg" and "mem" respectively.

- cdns,max-outbound-regions: Set to maximum number of outbound regions



Optional properties:

- max-functions: Maximum number of functions that can be configured (default 1).

- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more

  than one in the list.  If only one PHY listed it must manage all lanes. 

- phy-names:  List of names to identify the PHY.



Example:



pcie@fc000000 {

	compatible = "cdns,cdns-pcie-ep";

	reg = <0x0 0xfc000000 0x0 0x01000000>,

	      <0x0 0x80000000 0x0 0x40000000>;

	reg-names = "reg", "mem";

	cdns,max-outbound-regions = <16>;

	max-functions = /bits/ 8 <8>;

	phys = <&ep_phy0 &ep_phy1>;

	phy-names = "pcie-lane0","pcie-lane1";

};

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Cadence PCIe EP Controller



maintainers:

  - Tom Joseph <tjoseph@cadence.com>



allOf:

  - $ref: "cdns-pcie.yaml#"

  - $ref: "pci-ep.yaml#"



properties:

  compatible:

    const: cdns,cdns-pcie-ep



  reg:

    maxItems: 2



  reg-names:

    items:

      - const: reg

      - const: mem



required:

  - reg

  - reg-names



examples:

  - |

    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie-ep@fc000000 {

                compatible = "cdns,cdns-pcie-ep";

                reg = <0x0 0xfc000000 0x0 0x01000000>,

                      <0x0 0x80000000 0x0 0x40000000>;

                reg-names = "reg", "mem";

                cdns,max-outbound-regions = <16>;

                max-functions = /bits/ 8 <8>;

                phys = <&pcie_phy0>;

                phy-names = "pcie-phy";

        };

    };

...

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt

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* Cadence PCIe host controller



This PCIe controller inherits the base properties defined in

host-generic-pci.txt.



Required properties:

- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.

- reg: Should contain the controller register base address, PCIe configuration

  window base address, and AXI interface region base address respectively.

- reg-names: Must be "reg", "cfg" and "mem" respectively.

- #address-cells: Set to <3>

- #size-cells: Set to <2>

- device_type: Set to "pci"

- ranges: Ranges for the PCI memory and I/O regions

- #interrupt-cells: Set to <1>

- interrupt-map-mask and interrupt-map: Standard PCI properties to define the

  mapping of the PCIe interface to interrupt numbers.



Optional properties:

- cdns,max-outbound-regions: Set to maximum number of outbound regions

  (default 32)

- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the

  number of least significant bits kept during inbound (PCIe -> AXI) address

  translations (default 32)

- vendor-id: The PCI vendor ID (16 bits, default is design dependent)

- device-id: The PCI device ID (16 bits, default is design dependent)

- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more

  than one in the list.  If only one PHY listed it must manage all lanes. 

- phy-names:  List of names to identify the PHY.



Example:



pcie@fb000000 {

	compatible = "cdns,cdns-pcie-host";

	device_type = "pci";

	#address-cells = <3>;

	#size-cells = <2>;

	bus-range = <0x0 0xff>;

	linux,pci-domain = <0>;

	cdns,max-outbound-regions = <16>;

	cdns,no-bar-match-nbits = <32>;

	vendor-id = /bits/ 16 <0x17cd>;

	device-id = /bits/ 16 <0x0200>;



	reg = <0x0 0xfb000000  0x0 0x01000000>,

	      <0x0 0x41000000  0x0 0x00001000>,

	      <0x0 0x40000000  0x0 0x04000000>;

	reg-names = "reg", "cfg", "mem";



	ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,

		 <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;



	#interrupt-cells = <0x1>;



	interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1

			 0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1

			 0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1

			 0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;



	interrupt-map-mask = <0x0 0x0 0x0  0x7>;



	msi-parent = <&its_pci>;



	phys = <&pcie_phy0>;

	phy-names = "pcie-phy";

};

Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Cadence PCIe host controller



maintainers:

  - Tom Joseph <tjoseph@cadence.com>



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#

  - $ref: "cdns-pcie-host.yaml#"



properties:

  compatible:

    const: cdns,cdns-pcie-host



  reg:

    maxItems: 3



  reg-names:

    items:

      - const: reg

      - const: cfg

      - const: mem



  msi-parent: true



required:

  - reg

  - reg-names



examples:

  - |

    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@fb000000 {

            compatible = "cdns,cdns-pcie-host";

            device_type = "pci";

            #address-cells = <3>;

            #size-cells = <2>;

            bus-range = <0x0 0xff>;

            linux,pci-domain = <0>;

            cdns,max-outbound-regions = <16>;

            cdns,no-bar-match-nbits = <32>;

            vendor-id = <0x17cd>;

            device-id = <0x0200>;



            reg = <0x0 0xfb000000  0x0 0x01000000>,

                  <0x0 0x41000000  0x0 0x00001000>,

                  <0x0 0x40000000  0x0 0x04000000>;

            reg-names = "reg", "cfg", "mem";



            ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,

                     <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;



            #interrupt-cells = <0x1>;



            interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1>,

                 <0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1>,

                 <0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1>,

                 <0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;



            interrupt-map-mask = <0x0 0x0 0x0  0x7>;



            msi-parent = <&its_pci>;



            phys = <&pcie_phy0>;

            phy-names = "pcie-phy";

        };

    };

...

Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Cadence PCIe Host



maintainers:

  - Tom Joseph <tjoseph@cadence.com>



allOf:

  - $ref: "/schemas/pci/pci-bus.yaml#"

  - $ref: "cdns-pcie.yaml#"



properties:

  cdns,no-bar-match-nbits:

    description:

      Set into the no BAR match register to configure the number of least

      significant bits kept during inbound (PCIe -> AXI) address translations

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 64

    default: 32



  msi-parent: true

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