drm/nouveau/flcn/cmdq: move command generation to subdevs (86ce2a71) · Commits · 戴 / test

drivers/gpu/drm/nouveau/include/nvfw/pmu.h

0 → 100644

+47 −0

Original line number	Diff line number	Diff line
		#ifndef __NVFW_PMU_H__
		#define __NVFW_PMU_H__

		#define NV_PMU_UNIT_ACR 0x0a

		struct nv_pmu_acr_cmd {
		struct nv_falcon_cmd hdr;
		#define NV_PMU_ACR_CMD_INIT_WPR_REGION 0x00
		#define NV_PMU_ACR_CMD_BOOTSTRAP_FALCON 0x01
		#define NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS 0x03
		u8 cmd_type;
		};

		struct nv_pmu_acr_msg {
		struct nv_falcon_cmd hdr;
		u8 msg_type;
		};

		struct nv_pmu_acr_bootstrap_falcon_cmd {
		struct nv_pmu_acr_cmd cmd;
		#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
		#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
		u32 flags;
		u32 falcon_id;
		};

		struct nv_pmu_acr_bootstrap_falcon_msg {
		struct nv_pmu_acr_msg msg;
		u32 falcon_id;
		};

		struct nv_pmu_acr_bootstrap_multiple_falcons_cmd {
		struct nv_pmu_acr_cmd cmd;
		#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES 0x00000000
		#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_NO 0x00000001
		u32 flags;
		u32 falcon_mask;
		u32 use_va_mask;
		u32 wpr_lo;
		u32 wpr_hi;
		};

		struct nv_pmu_acr_bootstrap_multiple_falcons_msg {
		struct nv_pmu_acr_msg msg;
		u32 falcon_mask;
		};
		#endif

drivers/gpu/drm/nouveau/include/nvfw/sec2.h

0 → 100644

+30 −0

Original line number	Diff line number	Diff line
		#ifndef __NVFW_SEC2_H__
		#define __NVFW_SEC2_H__

		#define NV_SEC2_UNIT_ACR 0x08

		struct nv_sec2_acr_cmd {
		struct nv_falcon_cmd hdr;
		#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00
		u8 cmd_type;
		};

		struct nv_sec2_acr_msg {
		struct nv_falcon_cmd hdr;
		u8 msg_type;
		};

		struct nv_sec2_acr_bootstrap_falcon_cmd {
		struct nv_sec2_acr_cmd cmd;
		#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
		#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
		u32 flags;
		u32 falcon_id;
		};

		struct nv_sec2_acr_bootstrap_falcon_msg {
		struct nv_sec2_acr_msg msg;
		u32 error_code;
		u32 falcon_id;
		};
		#endif

drivers/gpu/drm/nouveau/include/nvkm/core/msgqueue.h

+0 −3

Original line number	Diff line number	Diff line
		@@ -37,7 +37,4 @@ int nvkm_msgqueue_reinit(struct nvkm_msgqueue *);
		/* useful if we run a NVIDIA-signed firmware */
		void nvkm_msgqueue_write_cmdline(struct nvkm_msgqueue , void );

		/* interface to ACR unit running on falcon (NVIDIA signed firmware) */
		int nvkm_msgqueue_acr_boot_falcons(struct nvkm_msgqueue *, unsigned long);

		#endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h

+22 −1

Original line number	Diff line number	Diff line
		@@ -13,15 +13,34 @@ enum nvkm_acr_lsf_id {
		NVKM_ACR_LSF_NVDEC = 4,
		NVKM_ACR_LSF_SEC2 = 7,
		NVKM_ACR_LSF_MINION = 10,
		NVKM_ACR_LSF_NUM
		};

		static inline const char *
		nvkm_acr_lsf_id(enum nvkm_acr_lsf_id id)
		{
		switch (id) {
		case NVKM_ACR_LSF_PMU : return "pmu";
		case NVKM_ACR_LSF_GSPLITE: return "gsplite";
		case NVKM_ACR_LSF_FECS : return "fecs";
		case NVKM_ACR_LSF_GPCCS : return "gpccs";
		case NVKM_ACR_LSF_NVDEC : return "nvdec";
		case NVKM_ACR_LSF_SEC2 : return "sec2";
		case NVKM_ACR_LSF_MINION : return "minion";
		default:
		return "unknown";
		}
		}

		struct nvkm_acr {
		const struct nvkm_acr_func *func;
		struct nvkm_subdev subdev;

		struct list_head lsfw;
		struct list_head lsfw, lsf;
		};

		int nvkm_acr_bootstrap_falcons(struct nvkm_device *, unsigned long mask);

		int gm200_acr_new(struct nvkm_device , int, struct nvkm_acr *);
		int gm20b_acr_new(struct nvkm_device , int, struct nvkm_acr *);
		int gp102_acr_new(struct nvkm_device , int, struct nvkm_acr *);
		@@ -55,6 +74,8 @@ struct nvkm_acr_lsfw {
		};

		struct nvkm_acr_lsf_func {
		int (bootstrap_falcon)(struct nvkm_falcon , enum nvkm_acr_lsf_id);
		int (bootstrap_multiple_falcons)(struct nvkm_falcon , u32 mask);
		};

		int

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

+44 −0

Original line number	Diff line number	Diff line
		@@ -20,11 +20,53 @@
		* DEALINGS IN THE SOFTWARE.
		*/
		#include "priv.h"

		#include <subdev/acr.h>
		#include <subdev/timer.h>

		#include <nvfw/sec2.h>

		static int
		gp102_sec2_acr_bootstrap_falcon_callback(void priv, struct nv_falcon_msg hdr)
		{
		struct nv_sec2_acr_bootstrap_falcon_msg *msg =
		container_of(hdr, typeof(*msg), msg.hdr);
		struct nvkm_subdev *subdev = priv;
		const char *name = nvkm_acr_lsf_id(msg->falcon_id);

		if (msg->error_code) {
		nvkm_error(subdev, "ACR_BOOTSTRAP_FALCON failed for "
		"falcon %d [%s]: %08x\n",
		msg->falcon_id, name, msg->error_code);
		return -EINVAL;
		}

		nvkm_debug(subdev, "%s booted\n", name);
		return 0;
		}

		static int
		gp102_sec2_acr_bootstrap_falcon(struct nvkm_falcon *falcon,
		enum nvkm_acr_lsf_id id)
		{
		struct nvkm_sec2 sec2 = container_of(falcon, typeof(sec2), falcon);
		struct nv_sec2_acr_bootstrap_falcon_cmd cmd = {
		.cmd.hdr.unit_id = sec2->func->unit_acr,
		.cmd.hdr.size = sizeof(cmd),
		.cmd.cmd_type = NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON,
		.flags = NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES,
		.falcon_id = id,
		};

		return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr,
		gp102_sec2_acr_bootstrap_falcon_callback,
		&sec2->engine.subdev,
		msecs_to_jiffies(1000));
		}

		static const struct nvkm_acr_lsf_func
		gp102_sec2_acr_0 = {
		.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
		};

		void
		@@ -117,6 +159,7 @@ gp102_sec2_flcn = {
		const struct nvkm_sec2_func
		gp102_sec2 = {
		.flcn = &gp102_sec2_flcn,
		.unit_acr = NV_SEC2_UNIT_ACR,
		.intr = gp102_sec2_intr,
		};

		@@ -135,6 +178,7 @@ MODULE_FIRMWARE("nvidia/gp107/sec2/sig.bin");

		const struct nvkm_acr_lsf_func
		gp102_sec2_acr_1 = {
		.bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon,
		};

		int

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