Commit 86cc3398 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "Two build fixes for a couple clk drivers and a fix for the Unisoc
  serial clk where we want to keep it on for earlycon"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sprd: don't gate uart console clock
  clk: mmp2: fix link error without mmp2
  clk: asm9260: fix __clk_hw_register_fixed_rate_with_accuracy typo
parents 0fe5f9ca ca6df49d
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ static void __init asm9260_acc_init(struct device_node *np)

	/* TODO: Convert to DT parent scheme */
	ref_clk = of_clk_get_parent_name(np, 0);
	hw = __clk_hw_register_fixed_rate_with_accuracy(NULL, NULL, pll_clk,
	hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk,
			ref_clk, NULL, NULL, 0, rate, 0,
			CLK_FIXED_RATE_PARENT_ACCURACY);

+32 −1
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ static const struct clk_ops mmp_clk_pll_ops = {
	.recalc_rate = mmp_clk_pll_recalc_rate,
};

struct clk *mmp_clk_register_pll(char *name,
static struct clk *mmp_clk_register_pll(char *name,
			unsigned long default_rate,
			void __iomem *enable_reg, u32 enable,
			void __iomem *reg, u8 shift,
@@ -137,3 +137,34 @@ struct clk *mmp_clk_register_pll(char *name,

	return clk;
}

void mmp_register_pll_clks(struct mmp_clk_unit *unit,
			struct mmp_param_pll_clk *clks,
			void __iomem *base, int size)
{
	struct clk *clk;
	int i;

	for (i = 0; i < size; i++) {
		void __iomem *reg = NULL;

		if (clks[i].offset)
			reg = base + clks[i].offset;

		clk = mmp_clk_register_pll(clks[i].name,
					clks[i].default_rate,
					base + clks[i].enable_offset,
					clks[i].enable,
					reg, clks[i].shift,
					clks[i].input_rate,
					base + clks[i].postdiv_offset,
					clks[i].postdiv_shift);
		if (IS_ERR(clk)) {
			pr_err("%s: failed to register clock %s\n",
			       __func__, clks[i].name);
			continue;
		}
		if (clks[i].id)
			unit->clk_table[clks[i].id] = clk;
	}
}
+0 −31
Original line number Diff line number Diff line
@@ -176,37 +176,6 @@ void mmp_register_div_clks(struct mmp_clk_unit *unit,
	}
}

void mmp_register_pll_clks(struct mmp_clk_unit *unit,
			struct mmp_param_pll_clk *clks,
			void __iomem *base, int size)
{
	struct clk *clk;
	int i;

	for (i = 0; i < size; i++) {
		void __iomem *reg = NULL;

		if (clks[i].offset)
			reg = base + clks[i].offset;

		clk = mmp_clk_register_pll(clks[i].name,
					clks[i].default_rate,
					base + clks[i].enable_offset,
					clks[i].enable,
					reg, clks[i].shift,
					clks[i].input_rate,
					base + clks[i].postdiv_offset,
					clks[i].postdiv_shift);
		if (IS_ERR(clk)) {
			pr_err("%s: failed to register clock %s\n",
			       __func__, clks[i].name);
			continue;
		}
		if (clks[i].id)
			unit->clk_table[clks[i].id] = clk;
	}
}

void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
			struct clk *clk)
{
+0 −7
Original line number Diff line number Diff line
@@ -238,13 +238,6 @@ void mmp_register_pll_clks(struct mmp_clk_unit *unit,
			struct mmp_param_pll_clk *clks,
			void __iomem *base, int size);

extern struct clk *mmp_clk_register_pll(char *name,
			unsigned long default_rate,
			void __iomem *enable_reg, u32 enable,
			void __iomem *reg, u8 shift,
			unsigned long input_rate,
			void __iomem *postdiv_reg, u8 postdiv_shift);

#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc)	\
{							\
	.width_div = (w_d),				\
+2 −1
Original line number Diff line number Diff line
@@ -1641,8 +1641,9 @@ static SPRD_SC_GATE_CLK_FW_NAME(i2c4_eb, "i2c4-eb", "ext-26m", 0x0,
				0x1000, BIT(12), 0, 0);
static SPRD_SC_GATE_CLK_FW_NAME(uart0_eb,	"uart0-eb",	"ext-26m", 0x0,
				0x1000, BIT(13), 0, 0);
/* uart1_eb is for console, don't gate even if unused */
static SPRD_SC_GATE_CLK_FW_NAME(uart1_eb,	"uart1-eb",	"ext-26m", 0x0,
				0x1000, BIT(14), 0, 0);
				0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
static SPRD_SC_GATE_CLK_FW_NAME(uart2_eb,	"uart2-eb",	"ext-26m", 0x0,
				0x1000, BIT(15), 0, 0);
static SPRD_SC_GATE_CLK_FW_NAME(uart3_eb,	"uart3-eb",	"ext-26m", 0x0,