clk: Support for clock parents and rates assigned from device tree (86be408b) · Commits · 戴 / test

Documentation/devicetree/bindings/clock/clock-bindings.txt

+36 −0

Original line number	Diff line number	Diff line
		@@ -131,3 +131,39 @@ clock signal, and a UART.
		("pll" and "pll-switched").
		* The UART has its baud clock connected the external oscillator and its
		register clock connected to the PLL clock (the "pll-switched" signal)

		==Assigned clock parents and rates==

		Some platforms may require initial configuration of default parent clocks
		and clock frequencies. Such a configuration can be specified in a device tree
		node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
		properties. The assigned-clock-parents property should contain a list of parent
		clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
		property the list of assigned clock frequency values - corresponding to clocks
		listed in the assigned-clocks property.

		To skip setting parent or rate of a clock its corresponding entry should be
		set to 0, or can be omitted if it is not followed by any non-zero entry.

		uart@a000 {
		compatible = "fsl,imx-uart";
		reg = <0xa000 0x1000>;
		...
		clocks = <&osc 0>, <&pll 1>;
		clock-names = "baud", "register";

		assigned-clocks = <&clkcon 0>, <&pll 2>;
		assigned-clock-parents = <&pll 2>;
		assigned-clock-rates = <0>, <460800>;
		};

		In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
		the <&pll 2> clock is assigned a frequency value of 460800 Hz.

		Configuring a clock's parent and rate through the device node that consumes
		the clock can be done only for clocks that have a single user. Specifying
		conflicting parent or rate configuration in multiple consumer nodes for
		a shared clock is forbidden.

		Configuration of common clocks, which affect multiple consumer devices can
		be similarly specified in the clock provider node.

drivers/base/platform.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@
		#include <linux/pm_runtime.h>
		#include <linux/idr.h>
		#include <linux/acpi.h>
		#include <linux/clk/clk-conf.h>

		#include "base.h"
		#include "power/power.h"
		@@ -489,6 +490,10 @@ static int platform_drv_probe(struct device *_dev)
		struct platform_device *dev = to_platform_device(_dev);
		int ret;

		ret = of_clk_set_defaults(_dev->of_node, false);
		if (ret < 0)
		return ret;

		acpi_dev_pm_attach(_dev, true);

		ret = drv->probe(dev);

drivers/clk/Makefile

+3 −0

Original line number	Diff line number	Diff line
		@@ -9,6 +9,9 @@ obj-$(CONFIG_COMMON_CLK) += clk-gate.o
		obj-$(CONFIG_COMMON_CLK) += clk-mux.o
		obj-$(CONFIG_COMMON_CLK) += clk-composite.o
		obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
		ifeq ($(CONFIG_OF), y)
		obj-$(CONFIG_COMMON_CLK) += clk-conf.o
		endif

		# hardware specific clock types
		# please keep this section sorted lexicographically by file/directory path name

drivers/clk/clk-conf.c

0 → 100644

+143 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (C) 2014 Samsung Electronics Co., Ltd.
		* Sylwester Nawrocki <s.nawrocki@samsung.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/

		#include <linux/clk.h>
		#include <linux/clk-provider.h>
		#include <linux/clk/clk-conf.h>
		#include <linux/device.h>
		#include <linux/of.h>
		#include <linux/printk.h>
		#include "clk.h"

		static int __set_clk_parents(struct device_node *node, bool clk_supplier)
		{
		struct of_phandle_args clkspec;
		int index, rc, num_parents;
		struct clk clk, pclk;

		num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
		"#clock-cells");
		if (num_parents == -EINVAL)
		pr_err("clk: invalid value of clock-parents property at %s\n",
		node->full_name);

		for (index = 0; index < num_parents; index++) {
		rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
		"#clock-cells", index, &clkspec);
		if (rc < 0) {
		/* skip empty (null) phandles */
		if (rc == -ENOENT)
		continue;
		else
		return rc;
		}
		if (clkspec.np == node && !clk_supplier)
		return 0;
		pclk = of_clk_get_by_clkspec(&clkspec);
		if (IS_ERR(pclk)) {
		pr_warn("clk: couldn't get parent clock %d for %s\n",
		index, node->full_name);
		return PTR_ERR(pclk);
		}

		rc = of_parse_phandle_with_args(node, "assigned-clocks",
		"#clock-cells", index, &clkspec);
		if (rc < 0)
		goto err;
		if (clkspec.np == node && !clk_supplier) {
		rc = 0;
		goto err;
		}
		clk = of_clk_get_by_clkspec(&clkspec);
		if (IS_ERR(pclk)) {
		pr_warn("clk: couldn't get parent clock %d for %s\n",
		index, node->full_name);
		rc = PTR_ERR(pclk);
		goto err;
		}

		rc = clk_set_parent(clk, pclk);
		if (rc < 0)
		pr_err("clk: failed to reparent %s to %s: %d\n",
		__clk_get_name(clk), __clk_get_name(pclk), rc);
		clk_put(clk);
		clk_put(pclk);
		}
		return 0;
		err:
		clk_put(pclk);
		return rc;
		}

		static int __set_clk_rates(struct device_node *node, bool clk_supplier)
		{
		struct of_phandle_args clkspec;
		struct property *prop;
		const __be32 *cur;
		int rc, index = 0;
		struct clk *clk;
		u32 rate;

		of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
		if (rate) {
		rc = of_parse_phandle_with_args(node, "assigned-clocks",
		"#clock-cells", index, &clkspec);
		if (rc < 0) {
		/* skip empty (null) phandles */
		if (rc == -ENOENT)
		continue;
		else
		return rc;
		}
		if (clkspec.np == node && !clk_supplier)
		return 0;

		clk = of_clk_get_by_clkspec(&clkspec);
		if (IS_ERR(clk)) {
		pr_warn("clk: couldn't get clock %d for %s\n",
		index, node->full_name);
		return PTR_ERR(clk);
		}

		rc = clk_set_rate(clk, rate);
		if (rc < 0)
		pr_err("clk: couldn't set %s clock rate: %d\n",
		__clk_get_name(clk), rc);
		clk_put(clk);
		}
		index++;
		}
		return 0;
		}

		/**
		* of_clk_set_defaults() - parse and set assigned clocks configuration
		* @node: device node to apply clock settings for
		* @clk_supplier: true if clocks supplied by @node should also be considered
		*
		* This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
		* and sets any specified clock parents and rates. The @clk_supplier argument
		* should be set to true if @node may be also a clock supplier of any clock
		* listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
		* If @clk_supplier is false the function exits returnning 0 as soon as it
		* determines the @node is also a supplier of any of the clocks.
		*/
		int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
		{
		int rc;

		if (!node)
		return 0;

		rc = __set_clk_parents(node, clk_supplier);
		if (rc < 0)
		return rc;

		return __set_clk_rates(node, clk_supplier);
		}

drivers/clk/clk.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@
		*/

		#include <linux/clk-private.h>
		#include <linux/clk/clk-conf.h>
		#include <linux/module.h>
		#include <linux/mutex.h>
		#include <linux/spinlock.h>
		@@ -2382,6 +2383,7 @@ int of_clk_add_provider(struct device_node *np,
		void *data)
		{
		struct of_clk_provider *cp;
		int ret;

		cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
		if (!cp)
		@@ -2396,7 +2398,11 @@ int of_clk_add_provider(struct device_node *np,
		mutex_unlock(&of_clk_mutex);
		pr_debug("Added clock from %s\n", np->full_name);

		return 0;
		ret = of_clk_set_defaults(np, true);
		if (ret < 0)
		of_clk_del_provider(np);

		return ret;
		}
		EXPORT_SYMBOL_GPL(of_clk_add_provider);

		@@ -2573,7 +2579,10 @@ void __init of_clk_init(const struct of_device_id *matches)
		list_for_each_entry_safe(clk_provider, next,
		&clk_provider_list, node) {
		if (force \|\| parent_ready(clk_provider->np)) {

		clk_provider->clk_init_cb(clk_provider->np);
		of_clk_set_defaults(clk_provider->np, true);

		list_del(&clk_provider->node);
		kfree(clk_provider);
		is_init_done = true;
		@@ -2588,7 +2597,6 @@ void __init of_clk_init(const struct of_device_id *matches)
		*/
		if (!is_init_done)
		force = true;

		}
		}
		#endif

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