Commit 8691c0db authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'socfpga/smp' into next/smp 



SMP support for socfpga platform, from Dinh Nguyen <dinguyen@altera.com>

v3:
-cleaned up socfpga_defconfig.
-Needs # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
-Removed CONFIG_VMSPLIT_2G, as system has 2GB of RAM
-Removed CONFIG_ARCH_TIMER
-Remove pen_release variable
-Added Reviewed-by: default avatarRob Herring <rob.herring@calxeda.com>

v2:
-Remove pen_release code
-Remove code that was already done by v7_setup
-Add bindings document for reset and system manager
-Move socfpga_sysmgr_init from platsmp.c to socfpga.c,
 because we will need to use the reset and system manager
 for more than SMP.
-Move core.h to mach-socfpga from mach-socfpga/include/mach

* socfpga/smp:
  ARM: socfpga: Enable SMP for socfpga

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 6f0c0580 9c4566a1

Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt

0 → 100644
+11 −0
Original line number Diff line number Diff line 
Altera SOCFPGA Reset Manager



Required properties:

- compatible : "altr,rst-mgr"

- reg : Should contain 1 register ranges(address and length)



Example:

	 rstmgr@ffd05000 {

		compatible = "altr,rst-mgr";

		reg = <0xffd05000 0x1000>;

	};

Documentation/devicetree/bindings/arm/altera/socfpga-system.txt

0 → 100644
+11 −0
Original line number Diff line number Diff line 
Altera SOCFPGA System Manager



Required properties:

- compatible : "altr,sys-mgr"

- reg : Should contain 1 register ranges(address and length)



Example:

	 sysmgr@ffd08000 {

		compatible = "altr,sys-mgr";

		reg = <0xffd08000 0x1000>;

	};

arch/arm/boot/dts/socfpga.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -143,5 +143,15 @@ 
			reg-shift = <2>;

			reg-io-width = <4>;

		};



		rstmgr@ffd05000 {

				compatible = "altr,rst-mgr";

				reg = <0xffd05000 0x1000>;

			};



		sysmgr@ffd08000 {

				compatible = "altr,sys-mgr";

				reg = <0xffd08000 0x4000>;

			};

	};

};

arch/arm/configs/socfpga_defconfig

+2 −1
Original line number Diff line number Diff line
@@ -18,9 +18,10 @@ CONFIG_MODULE_UNLOAD=y 
CONFIG_ARCH_SOCFPGA=y

CONFIG_MACH_SOCFPGA_CYCLONE5=y

CONFIG_ARM_THUMBEE=y

# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set

# CONFIG_CACHE_L2X0 is not set

CONFIG_HIGH_RES_TIMERS=y

CONFIG_VMSPLIT_2G=y

CONFIG_SMP=y

CONFIG_NR_CPUS=2

CONFIG_AEABI=y

CONFIG_ZBOOT_ROM_TEXT=0x0

arch/arm/mach-socfpga/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -12,5 +12,6 @@ config ARCH_SOCFPGA 
	select GENERIC_CLOCKEVENTS

	select GPIO_PL061 if GPIOLIB

	select HAVE_ARM_SCU

	select HAVE_SMP

	select SPARSE_IRQ

	select USE_OF

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