Commit 86444413 authored Jul 03, 2020 by Chao Hao Committed by Joerg Roedel Jul 10, 2020

iommu/mediatek: Modify MMU_CTRL register setting



The MMU_CTRL register of MT8173 is different from other SoCs.
The in_order_wr_en is bit[9] which is zero by default.
Other SoCs have the vitcim_tlb_en feature mapped to bit[12].
This bit is set to one by default. We need to preserve the bit
when setting F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the
bit will be cleared and IOMMU performance will drop.

Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Yong Wu <yong.wu@mediatek.com>
Link: https://lore.kernel.org/r/20200703044127.27438-10-chao.hao@mediatek.com


Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent 829316b3

drivers/iommu/mtk_iommu.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -555,11 +555,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
		return ret;
		}

		if (data->plat_data->m4u_plat == M4U_MT8173)
		if (data->plat_data->m4u_plat == M4U_MT8173) {
		regval = F_MMU_PREFETCH_RT_REPLACE_MOD \|
		F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
		else
		regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
		} else {
		regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
		regval \|= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
		}
		writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);

		regval = F_L2_MULIT_HIT_EN \|

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