Merge series "ASoC: Mediatek: Add support for MT8192 SoC" from Jiaxin Yu <jiaxin.yu@mediatek.com>: (860bfa6d) · Commits · 戴 / test

Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Mediatek AFE PCM controller for mt8192

		maintainers:
		- Jiaxin Yu <jiaxin.yu@mediatek.com>
		- Shane Chien <shane.chien@mediatek.com>

		properties:
		compatible:
		const: mediatek,mt8192-audio

		interrupts:
		maxItems: 1

		resets:
		maxItems: 1

		reset-names:
		const: audiosys

		mediatek,apmixedsys:
		$ref: "/schemas/types.yaml#/definitions/phandle"
		description: The phandle of the mediatek apmixedsys controller

		mediatek,infracfg:
		$ref: "/schemas/types.yaml#/definitions/phandle"
		description: The phandle of the mediatek infracfg controller

		mediatek,topckgen:
		$ref: "/schemas/types.yaml#/definitions/phandle"
		description: The phandle of the mediatek topckgen controller

		power-domains:
		maxItems: 1

		clocks:
		items:
		- description: AFE clock
		- description: ADDA DAC clock
		- description: ADDA DAC pre-distortion clock
		- description: audio infra sys clock
		- description: audio infra 26M clock

		clock-names:
		items:
		- const: aud_afe_clk
		- const: aud_dac_clk
		- const: aud_dac_predis_clk
		- const: aud_infra_clk
		- const: aud_infra_26m_clk

		required:
		- compatible
		- interrupts
		- resets
		- reset-names
		- mediatek,apmixedsys
		- mediatek,infracfg
		- mediatek,topckgen
		- power-domains
		- clocks
		- clock-names

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/mt8192-clk.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/interrupt-controller/irq.h>
		#include <dt-bindings/power/mt8192-power.h>
		#include <dt-bindings/reset-controller/mt8192-resets.h>

		afe: mt8192-afe-pcm {
		compatible = "mediatek,mt8192-audio";
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
		reset-names = "audiosys";
		mediatek,apmixedsys = <&apmixedsys>;
		mediatek,infracfg = <&infracfg>;
		mediatek,topckgen = <&topckgen>;
		power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
		clocks = <&audsys CLK_AUD_AFE>,
		<&audsys CLK_AUD_DAC>,
		<&audsys CLK_AUD_DAC_PREDIS>,
		<&infracfg CLK_INFRA_AUDIO>,
		<&infracfg CLK_INFRA_AUDIO_26M_B>;
		clock-names = "aud_afe_clk",
		"aud_dac_clk",
		"aud_dac_predis_clk",
		"aud_infra_clk",
		"aud_infra_26m_clk";
		};

		...

Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/sound/mt8192-mt6359-rt1015-rt5682.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Mediatek MT8192 with MT6359, RT1015 and RT5682 ASoC sound card driver

		maintainers:
		- Jiaxin Yu <jiaxin.yu@mediatek.com>
		- Shane Chien <shane.chien@mediatek.com>

		description:
		This binding describes the MT8192 sound card.

		properties:
		compatible:
		const: mediatek,mt8192_mt6359_rt1015_rt5682

		mediatek,platform:
		$ref: "/schemas/types.yaml#/definitions/phandle"
		description: The phandle of MT8192 ASoC platform.

		additionalProperties: false

		required:
		- compatible
		- mediatek,platform

		examples:
		- \|

		sound: mt8192-sound {
		compatible = "mediatek,mt8192-mt6359-rt1015-rt5682";
		mediatek,platform = <&afe>;
		pinctrl-names = "aud_clk_mosi_off",
		"aud_clk_mosi_on";
		pinctrl-0 = <&aud_clk_mosi_off>;
		pinctrl-1 = <&aud_clk_mosi_on>;
		};

		...

sound/soc/codecs/mt6359.c

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		@@ -68,6 +68,38 @@ static void mt6359_reset_capture_gpio(struct mt6359_priv *priv)
		0x3 << 0, 0x0);
		}

		/* use only when doing mtkaif calibraiton at the boot time */
		static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
		{
		regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
		0x1 << RG_XO_AUDIO_EN_M_SFT,
		(enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
		}

		/* use only when doing mtkaif calibraiton at the boot time */
		static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
		{
		/* Enable/disable CLKSQ 26MHz */
		regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
		RG_CLKSQ_EN_MASK_SFT,
		(enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
		}

		/* use only when doing mtkaif calibraiton at the boot time */
		static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
		{
		regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
		RG_AUDGLB_PWRDN_VA32_MASK_SFT,
		(enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT);
		}

		/* use only when doing mtkaif calibraiton at the boot time */
		static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)
		{
		regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
		0x0066, enable ? 0x0 : 0x66);
		}

		static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
		{
		regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
		@@ -122,6 +154,84 @@ static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
		0xff00, 0x3000);
		}

		void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
		int mtkaif_protocol)
		{
		struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);

		priv->mtkaif_protocol = mtkaif_protocol;
		}
		EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_protocol);

		void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
		{
		struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);

		mt6359_set_playback_gpio(priv);
		mt6359_set_capture_gpio(priv);
		mt6359_mtkaif_tx_enable(priv);

		mt6359_set_dcxo(priv, true);
		mt6359_set_aud_global_bias(priv, true);
		mt6359_set_clksq(priv, true);
		mt6359_set_topck(priv, true);

		/* set dat_miso_loopback on */
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
		RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
		1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
		RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
		1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
		RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
		1 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
		}
		EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_enable);

		void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
		{
		struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);

		/* set dat_miso_loopback off */
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
		RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
		0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
		RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
		0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
		RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
		0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);

		mt6359_set_topck(priv, false);
		mt6359_set_clksq(priv, false);
		mt6359_set_aud_global_bias(priv, false);
		mt6359_set_dcxo(priv, false);

		mt6359_mtkaif_tx_disable(priv);
		mt6359_reset_playback_gpio(priv);
		mt6359_reset_capture_gpio(priv);
		}
		EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_disable);

		void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
		int phase_1, int phase_2, int phase_3)
		{
		struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);

		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
		RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
		phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
		RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
		phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
		regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
		RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT,
		phase_3 << RG_AUD_PAD_TOP_PHASE_MODE3_SFT);
		}
		EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_calibration_phase);

		static void zcd_disable(struct mt6359_priv *priv)
		{
		regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);

sound/soc/codecs/mt6359.h

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		@@ -2637,4 +2637,11 @@ struct mt6359_priv {
		(type) == MIC_TYPE_MUX_DCC_ECM_DIFF \|\| \
		(type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)

		void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
		int mtkaif_protocol);
		void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt);
		void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt);
		void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
		int phase_1, int phase_2, int phase_3);

		#endif/* end _MT6359_H_ */

sound/soc/mediatek/Kconfig

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		@@ -158,3 +158,26 @@ config SND_SOC_MTK_BTCVSD
		BT encoded data to/from BT firmware.
		Select Y if you have such device.
		If unsure select "N".

		config SND_SOC_MT8192
		tristate "ASoC support for Mediatek MT8192 chip"
		depends on ARCH_MEDIATEK
		select SND_SOC_MEDIATEK
		help
		This adds ASoC platform driver support for Mediatek MT8192 chip
		that can be used with other codecs.
		Select Y if you have such device.
		If unsure select "N".

		config SND_SOC_MT8192_MT6359_RT1015_RT5682
		tristate "ASoC Audio driver for MT8192 with MT6359 RT1015 RT5682 codec"
		depends on I2C
		depends on SND_SOC_MT8192
		select SND_SOC_MT6359
		select SND_SOC_RT1015
		select SND_SOC_RT5682_I2C
		help
		This adds ASoC driver for Mediatek MT8192 boards
		with the MT6359 RT1015 RT5682 audio codec.
		Select Y if you have such device.
		If unsure select "N".

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